radeonsi/gfx10: simplify a streamout loop in gfx10_emit_ngg_epilogue

[mesa.git] / src / gallium / drivers / swr / swr_clear.cpp

diff --git a/src/gallium/drivers/swr/swr_clear.cpp b/src/gallium/drivers/swr/swr_clear.cpp
index ff3eca85f00c3d906be52f8ce897f6a899d9ff22..3e02bda19c9b04b41462ee67231b985f1defcab9 100644 (file)
--- a/src/gallium/drivers/swr/swr_clear.cpp
+++ b/src/gallium/drivers/swr/swr_clear.cpp
@@ -35,6 +35,7 @@ swr_clear(struct pipe_context *pipe,
    struct pipe_framebuffer_state *fb = &ctx->framebuffer;
 
    UINT clearMask = 0;
+   unsigned layers = 0;
 
    if (!swr_check_render_cond(pipe))
       return;
@@ -43,24 +44,54 @@ swr_clear(struct pipe_context *pipe,
 
    if (buffers & PIPE_CLEAR_COLOR && fb->nr_cbufs) {
       for (unsigned i = 0; i < fb->nr_cbufs; ++i)
-         if (fb->cbufs[i])
+         if (fb->cbufs[i] && (buffers & (PIPE_CLEAR_COLOR0 << i))) {
             clearMask |= (SWR_ATTACHMENT_COLOR0_BIT << i);
+            layers = std::max(layers, fb->cbufs[i]->u.tex.last_layer -
+                                      fb->cbufs[i]->u.tex.first_layer + 1u);
+         }
    }
 
-   if (buffers & PIPE_CLEAR_DEPTH && fb->zsbuf)
+   if (buffers & PIPE_CLEAR_DEPTH && fb->zsbuf) {
       clearMask |= SWR_ATTACHMENT_DEPTH_BIT;
+      layers = std::max(layers, fb->zsbuf->u.tex.last_layer -
+                                fb->zsbuf->u.tex.first_layer + 1u);
+   }
 
-   if (buffers & PIPE_CLEAR_STENCIL && fb->zsbuf)
+   if (buffers & PIPE_CLEAR_STENCIL && fb->zsbuf) {
       clearMask |= SWR_ATTACHMENT_STENCIL_BIT;
+      layers = std::max(layers, fb->zsbuf->u.tex.last_layer -
+                                fb->zsbuf->u.tex.first_layer + 1u);
+   }
 
 #if 0 // XXX HACK, override clear color alpha. On ubuntu, clears are
       // transparent.
    ((union pipe_color_union *)color)->f[3] = 1.0; /* cast off your const'd-ness */
 #endif
 
-   swr_update_draw_context(ctx);
-   SwrClearRenderTarget(ctx->swrContext, clearMask, color->f, depth, stencil,
-                        ctx->swr_scissor);
+   SWR_RECT clear_rect;
+   /* If enabled, clear to scissor; otherwise clear full surface */
+   if (ctx->rasterizer && ctx->rasterizer->scissor) {
+      clear_rect = ctx->swr_scissors[0];
+   } else {
+      clear_rect = {0, 0, (int32_t)fb->width, (int32_t)fb->height};
+   }
+
+   for (unsigned i = 0; i < layers; ++i) {
+      swr_update_draw_context(ctx);
+      ctx->api.pfnSwrClearRenderTarget(ctx->swrContext, clearMask, i,
+                                       color->f, depth, stencil,
+                                       clear_rect);
+
+      // Mask out the attachments that are out of layers.
+      if (fb->zsbuf &&
+          (fb->zsbuf->u.tex.last_layer <= fb->zsbuf->u.tex.first_layer + i))
+         clearMask &= ~(SWR_ATTACHMENT_DEPTH_BIT | SWR_ATTACHMENT_STENCIL_BIT);
+      for (unsigned c = 0; c < fb->nr_cbufs; ++c) {
+         const struct pipe_surface *sf = fb->cbufs[c];
+         if (sf && (sf->u.tex.last_layer <= sf->u.tex.first_layer + i))
+            clearMask &= ~(SWR_ATTACHMENT_COLOR0_BIT << c);
+      }
+   }
 }