* IN THE SOFTWARE.
***************************************************************************/
+#include "swr_context.h"
+#include "swr_public.h"
+#include "swr_screen.h"
+#include "swr_resource.h"
+#include "swr_fence.h"
+#include "gen_knobs.h"
+
#include "pipe/p_screen.h"
#include "pipe/p_defines.h"
#include "util/u_memory.h"
#include "gallivm/lp_bld_limits.h"
}
-#include "swr_public.h"
-#include "swr_screen.h"
-#include "swr_context.h"
-#include "swr_resource.h"
-#include "swr_fence.h"
-#include "gen_knobs.h"
-
#include "jit_api.h"
+#include "memory/TilingFunctions.h"
+
#include <stdio.h>
#include <map>
case PIPE_CAP_PRIMITIVE_RESTART:
return 1;
case PIPE_CAP_SHADER_STENCIL_EXPORT:
- return 1;
+ return 0;
case PIPE_CAP_TGSI_INSTANCEID:
case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
case PIPE_CAP_START_INSTANCE:
case PIPE_CAP_TEXTURE_BARRIER:
return 0;
case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
- case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: /* draw module */
- case PIPE_CAP_VERTEX_COLOR_CLAMPED: /* draw module */
+ case PIPE_CAP_VERTEX_COLOR_CLAMPED:
+ return 0;
+ case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
return 1;
case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
return 1;
case PIPE_CAP_USER_INDEX_BUFFERS:
case PIPE_CAP_USER_CONSTANT_BUFFERS:
case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
- case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
+ case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
return 1;
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
return 16;
+ case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
return 0;
case PIPE_CAP_DEPTH_BOUNDS_TEST:
- return 0; // xxx
+ return 1;
case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
return 1;
mesa_to_swr_format(enum pipe_format format)
{
static const std::map<pipe_format,SWR_FORMAT> mesa2swr = {
- {PIPE_FORMAT_NONE, (SWR_FORMAT)-1},
{PIPE_FORMAT_B8G8R8A8_UNORM, B8G8R8A8_UNORM},
{PIPE_FORMAT_B8G8R8X8_UNORM, B8G8R8X8_UNORM},
- {PIPE_FORMAT_A8R8G8B8_UNORM, (SWR_FORMAT)-1},
- {PIPE_FORMAT_X8R8G8B8_UNORM, (SWR_FORMAT)-1},
{PIPE_FORMAT_B5G5R5A1_UNORM, B5G5R5A1_UNORM},
{PIPE_FORMAT_B4G4R4A4_UNORM, B4G4R4A4_UNORM},
{PIPE_FORMAT_B5G6R5_UNORM, B5G6R5_UNORM},
{PIPE_FORMAT_R10G10B10A2_UNORM, R10G10B10A2_UNORM},
- {PIPE_FORMAT_L8_UNORM, L8_UNORM},
{PIPE_FORMAT_A8_UNORM, A8_UNORM},
- {PIPE_FORMAT_I8_UNORM, I8_UNORM},
- {PIPE_FORMAT_L8A8_UNORM, L8A8_UNORM},
- {PIPE_FORMAT_L16_UNORM, L16_UNORM},
- {PIPE_FORMAT_UYVY, YCRCB_SWAPUVY},
- {PIPE_FORMAT_YUYV, (SWR_FORMAT)-1},
{PIPE_FORMAT_Z16_UNORM, R16_UNORM}, // z
- {PIPE_FORMAT_Z32_UNORM, (SWR_FORMAT)-1},
{PIPE_FORMAT_Z32_FLOAT, R32_FLOAT}, // z
{PIPE_FORMAT_Z24_UNORM_S8_UINT, R24_UNORM_X8_TYPELESS}, // z
- {PIPE_FORMAT_S8_UINT_Z24_UNORM, (SWR_FORMAT)-1},
{PIPE_FORMAT_Z24X8_UNORM, R24_UNORM_X8_TYPELESS}, // z
- {PIPE_FORMAT_X8Z24_UNORM, (SWR_FORMAT)-1},
- {PIPE_FORMAT_S8_UINT, (SWR_FORMAT)-1},
- {PIPE_FORMAT_R64_FLOAT, (SWR_FORMAT)-1},
- {PIPE_FORMAT_R64G64_FLOAT, (SWR_FORMAT)-1},
- {PIPE_FORMAT_R64G64B64_FLOAT, (SWR_FORMAT)-1},
- {PIPE_FORMAT_R64G64B64A64_FLOAT, (SWR_FORMAT)-1},
{PIPE_FORMAT_R32_FLOAT, R32_FLOAT},
{PIPE_FORMAT_R32G32_FLOAT, R32G32_FLOAT},
{PIPE_FORMAT_R32G32B32_FLOAT, R32G32B32_FLOAT},
{PIPE_FORMAT_R32G32B32A32_FLOAT, R32G32B32A32_FLOAT},
- {PIPE_FORMAT_R32_UNORM, (SWR_FORMAT)-1},
- {PIPE_FORMAT_R32G32_UNORM, (SWR_FORMAT)-1},
- {PIPE_FORMAT_R32G32B32_UNORM, (SWR_FORMAT)-1},
- {PIPE_FORMAT_R32G32B32A32_UNORM, (SWR_FORMAT)-1},
{PIPE_FORMAT_R32_USCALED, R32_USCALED},
{PIPE_FORMAT_R32G32_USCALED, R32G32_USCALED},
{PIPE_FORMAT_R32G32B32_USCALED, R32G32B32_USCALED},
{PIPE_FORMAT_R32G32B32A32_USCALED, R32G32B32A32_USCALED},
- {PIPE_FORMAT_R32_SNORM, (SWR_FORMAT)-1},
- {PIPE_FORMAT_R32G32_SNORM, (SWR_FORMAT)-1},
- {PIPE_FORMAT_R32G32B32_SNORM, (SWR_FORMAT)-1},
- {PIPE_FORMAT_R32G32B32A32_SNORM, (SWR_FORMAT)-1},
{PIPE_FORMAT_R32_SSCALED, R32_SSCALED},
{PIPE_FORMAT_R32G32_SSCALED, R32G32_SSCALED},
{PIPE_FORMAT_R32G32B32_SSCALED, R32G32B32_SSCALED},
{PIPE_FORMAT_R8G8_UNORM, R8G8_UNORM},
{PIPE_FORMAT_R8G8B8_UNORM, R8G8B8_UNORM},
{PIPE_FORMAT_R8G8B8A8_UNORM, R8G8B8A8_UNORM},
- {PIPE_FORMAT_X8B8G8R8_UNORM, (SWR_FORMAT)-1},
{PIPE_FORMAT_R8_USCALED, R8_USCALED},
{PIPE_FORMAT_R8G8_USCALED, R8G8_USCALED},
{PIPE_FORMAT_R8G8B8_USCALED, R8G8B8_USCALED},
{PIPE_FORMAT_R8G8_SSCALED, R8G8_SSCALED},
{PIPE_FORMAT_R8G8B8_SSCALED, R8G8B8_SSCALED},
{PIPE_FORMAT_R8G8B8A8_SSCALED, R8G8B8A8_SSCALED},
- {PIPE_FORMAT_R32_FIXED, (SWR_FORMAT)-1},
- {PIPE_FORMAT_R32G32_FIXED, (SWR_FORMAT)-1},
- {PIPE_FORMAT_R32G32B32_FIXED, (SWR_FORMAT)-1},
- {PIPE_FORMAT_R32G32B32A32_FIXED, (SWR_FORMAT)-1},
{PIPE_FORMAT_R16_FLOAT, R16_FLOAT},
{PIPE_FORMAT_R16G16_FLOAT, R16G16_FLOAT},
{PIPE_FORMAT_R16G16B16_FLOAT, R16G16B16_FLOAT},
{PIPE_FORMAT_R16G16B16A16_FLOAT, R16G16B16A16_FLOAT},
- {PIPE_FORMAT_L8_SRGB, L8_UNORM_SRGB},
- {PIPE_FORMAT_L8A8_SRGB, L8A8_UNORM_SRGB},
{PIPE_FORMAT_R8G8B8_SRGB, R8G8B8_UNORM_SRGB},
- {PIPE_FORMAT_A8B8G8R8_SRGB, (SWR_FORMAT)-1},
- {PIPE_FORMAT_X8B8G8R8_SRGB, (SWR_FORMAT)-1},
{PIPE_FORMAT_B8G8R8A8_SRGB, B8G8R8A8_UNORM_SRGB},
{PIPE_FORMAT_B8G8R8X8_SRGB, B8G8R8X8_UNORM_SRGB},
- {PIPE_FORMAT_A8R8G8B8_SRGB, (SWR_FORMAT)-1},
- {PIPE_FORMAT_X8R8G8B8_SRGB, (SWR_FORMAT)-1},
{PIPE_FORMAT_R8G8B8A8_SRGB, R8G8B8A8_UNORM_SRGB},
- {PIPE_FORMAT_DXT1_RGB, (SWR_FORMAT)-1},
- {PIPE_FORMAT_DXT1_RGBA, BC1_UNORM},
- {PIPE_FORMAT_DXT3_RGBA, BC2_UNORM},
- {PIPE_FORMAT_DXT5_RGBA, BC3_UNORM},
-
- {PIPE_FORMAT_DXT1_SRGB, (SWR_FORMAT)-1},
- {PIPE_FORMAT_DXT1_SRGBA, BC1_UNORM_SRGB},
- {PIPE_FORMAT_DXT3_SRGBA, BC2_UNORM_SRGB},
- {PIPE_FORMAT_DXT5_SRGBA, BC3_UNORM_SRGB},
-
- {PIPE_FORMAT_RGTC1_UNORM, BC4_UNORM},
- {PIPE_FORMAT_RGTC1_SNORM, BC4_SNORM},
- {PIPE_FORMAT_RGTC2_UNORM, BC5_UNORM},
- {PIPE_FORMAT_RGTC2_SNORM, BC5_SNORM},
-
- {PIPE_FORMAT_R8G8_B8G8_UNORM, (SWR_FORMAT)-1},
- {PIPE_FORMAT_G8R8_G8B8_UNORM, (SWR_FORMAT)-1},
-
- {PIPE_FORMAT_R8SG8SB8UX8U_NORM, (SWR_FORMAT)-1},
- {PIPE_FORMAT_R5SG5SB6U_NORM, (SWR_FORMAT)-1},
-
- {PIPE_FORMAT_A8B8G8R8_UNORM, (SWR_FORMAT)-1},
{PIPE_FORMAT_B5G5R5X1_UNORM, B5G5R5X1_UNORM},
{PIPE_FORMAT_R10G10B10A2_USCALED, R10G10B10A2_USCALED},
{PIPE_FORMAT_R11G11B10_FLOAT, R11G11B10_FLOAT},
- {PIPE_FORMAT_R9G9B9E5_FLOAT, R9G9B9E5_SHAREDEXP},
{PIPE_FORMAT_Z32_FLOAT_S8X24_UINT, R32_FLOAT_X8X24_TYPELESS}, // z
- {PIPE_FORMAT_R1_UNORM, (SWR_FORMAT)-1},
{PIPE_FORMAT_R10G10B10X2_USCALED, R10G10B10X2_USCALED},
- {PIPE_FORMAT_R10G10B10X2_SNORM, (SWR_FORMAT)-1},
- {PIPE_FORMAT_L4A4_UNORM, (SWR_FORMAT)-1},
{PIPE_FORMAT_B10G10R10A2_UNORM, B10G10R10A2_UNORM},
- {PIPE_FORMAT_R10SG10SB10SA2U_NORM, (SWR_FORMAT)-1},
- {PIPE_FORMAT_R8G8Bx_SNORM, (SWR_FORMAT)-1},
{PIPE_FORMAT_R8G8B8X8_UNORM, R8G8B8X8_UNORM},
- {PIPE_FORMAT_B4G4R4X4_UNORM, (SWR_FORMAT)-1},
- {PIPE_FORMAT_X24S8_UINT, (SWR_FORMAT)-1},
- {PIPE_FORMAT_S8X24_UINT, (SWR_FORMAT)-1},
- {PIPE_FORMAT_X32_S8X24_UINT, (SWR_FORMAT)-1},
-
- {PIPE_FORMAT_B2G3R3_UNORM, (SWR_FORMAT)-1},
- {PIPE_FORMAT_L16A16_UNORM, L16A16_UNORM},
{PIPE_FORMAT_A16_UNORM, A16_UNORM},
- {PIPE_FORMAT_I16_UNORM, I16_UNORM},
-
- {PIPE_FORMAT_LATC1_UNORM, (SWR_FORMAT)-1},
- {PIPE_FORMAT_LATC1_SNORM, (SWR_FORMAT)-1},
- {PIPE_FORMAT_LATC2_UNORM, (SWR_FORMAT)-1},
- {PIPE_FORMAT_LATC2_SNORM, (SWR_FORMAT)-1},
-
- {PIPE_FORMAT_A8_SNORM, (SWR_FORMAT)-1},
- {PIPE_FORMAT_L8_SNORM, (SWR_FORMAT)-1},
- {PIPE_FORMAT_L8A8_SNORM, (SWR_FORMAT)-1},
- {PIPE_FORMAT_I8_SNORM, (SWR_FORMAT)-1},
- {PIPE_FORMAT_A16_SNORM, (SWR_FORMAT)-1},
- {PIPE_FORMAT_L16_SNORM, (SWR_FORMAT)-1},
- {PIPE_FORMAT_L16A16_SNORM, (SWR_FORMAT)-1},
- {PIPE_FORMAT_I16_SNORM, (SWR_FORMAT)-1},
-
{PIPE_FORMAT_A16_FLOAT, A16_FLOAT},
- {PIPE_FORMAT_L16_FLOAT, L16_FLOAT},
- {PIPE_FORMAT_L16A16_FLOAT, L16A16_FLOAT},
- {PIPE_FORMAT_I16_FLOAT, I16_FLOAT},
{PIPE_FORMAT_A32_FLOAT, A32_FLOAT},
- {PIPE_FORMAT_L32_FLOAT, L32_FLOAT},
- {PIPE_FORMAT_L32A32_FLOAT, L32A32_FLOAT},
- {PIPE_FORMAT_I32_FLOAT, I32_FLOAT},
-
- {PIPE_FORMAT_YV12, (SWR_FORMAT)-1},
- {PIPE_FORMAT_YV16, (SWR_FORMAT)-1},
- {PIPE_FORMAT_IYUV, (SWR_FORMAT)-1},
- {PIPE_FORMAT_NV12, (SWR_FORMAT)-1},
- {PIPE_FORMAT_NV21, (SWR_FORMAT)-1},
-
- {PIPE_FORMAT_A4R4_UNORM, (SWR_FORMAT)-1},
- {PIPE_FORMAT_R4A4_UNORM, (SWR_FORMAT)-1},
- {PIPE_FORMAT_R8A8_UNORM, (SWR_FORMAT)-1},
- {PIPE_FORMAT_A8R8_UNORM, (SWR_FORMAT)-1},
{PIPE_FORMAT_R10G10B10A2_SSCALED, R10G10B10A2_SSCALED},
{PIPE_FORMAT_R10G10B10A2_SNORM, R10G10B10A2_SNORM},
{PIPE_FORMAT_R32G32B32_SINT, R32G32B32_SINT},
{PIPE_FORMAT_R32G32B32A32_SINT, R32G32B32A32_SINT},
- {PIPE_FORMAT_A8_UINT, (SWR_FORMAT)-1},
- {PIPE_FORMAT_I8_UINT, I8_UINT},
- {PIPE_FORMAT_L8_UINT, L8_UINT},
- {PIPE_FORMAT_L8A8_UINT, L8A8_UINT},
+ {PIPE_FORMAT_B10G10R10A2_UINT, B10G10R10A2_UINT},
- {PIPE_FORMAT_A8_SINT, (SWR_FORMAT)-1},
- {PIPE_FORMAT_I8_SINT, I8_SINT},
- {PIPE_FORMAT_L8_SINT, L8_SINT},
- {PIPE_FORMAT_L8A8_SINT, L8A8_SINT},
+ {PIPE_FORMAT_B10G10R10X2_UNORM, B10G10R10X2_UNORM},
+ {PIPE_FORMAT_R16G16B16X16_UNORM, R16G16B16X16_UNORM},
+ {PIPE_FORMAT_R16G16B16X16_FLOAT, R16G16B16X16_FLOAT},
+ {PIPE_FORMAT_R32G32B32X32_FLOAT, R32G32B32X32_FLOAT},
+ {PIPE_FORMAT_R10G10B10A2_UINT, R10G10B10A2_UINT},
- {PIPE_FORMAT_A16_UINT, (SWR_FORMAT)-1},
- {PIPE_FORMAT_I16_UINT, (SWR_FORMAT)-1},
- {PIPE_FORMAT_L16_UINT, (SWR_FORMAT)-1},
- {PIPE_FORMAT_L16A16_UINT, (SWR_FORMAT)-1},
+ {PIPE_FORMAT_B5G6R5_SRGB, B5G6R5_UNORM_SRGB},
- {PIPE_FORMAT_A16_SINT, (SWR_FORMAT)-1},
- {PIPE_FORMAT_I16_SINT, (SWR_FORMAT)-1},
- {PIPE_FORMAT_L16_SINT, (SWR_FORMAT)-1},
- {PIPE_FORMAT_L16A16_SINT, (SWR_FORMAT)-1},
+ /* These formats have entries in SWR but don't have Load/StoreTile
+ * implementations. That means these aren't renderable, and thus having
+ * a mapping entry here is detrimental.
+ */
+ /*
- {PIPE_FORMAT_A32_UINT, (SWR_FORMAT)-1},
- {PIPE_FORMAT_I32_UINT, (SWR_FORMAT)-1},
- {PIPE_FORMAT_L32_UINT, (SWR_FORMAT)-1},
- {PIPE_FORMAT_L32A32_UINT, (SWR_FORMAT)-1},
+ {PIPE_FORMAT_L8_UNORM, L8_UNORM},
+ {PIPE_FORMAT_I8_UNORM, I8_UNORM},
+ {PIPE_FORMAT_L8A8_UNORM, L8A8_UNORM},
+ {PIPE_FORMAT_L16_UNORM, L16_UNORM},
+ {PIPE_FORMAT_UYVY, YCRCB_SWAPUVY},
- {PIPE_FORMAT_A32_SINT, (SWR_FORMAT)-1},
- {PIPE_FORMAT_I32_SINT, (SWR_FORMAT)-1},
- {PIPE_FORMAT_L32_SINT, (SWR_FORMAT)-1},
- {PIPE_FORMAT_L32A32_SINT, (SWR_FORMAT)-1},
+ {PIPE_FORMAT_L8_SRGB, L8_UNORM_SRGB},
+ {PIPE_FORMAT_L8A8_SRGB, L8A8_UNORM_SRGB},
- {PIPE_FORMAT_B10G10R10A2_UINT, B10G10R10A2_UINT},
+ {PIPE_FORMAT_DXT1_RGBA, BC1_UNORM},
+ {PIPE_FORMAT_DXT3_RGBA, BC2_UNORM},
+ {PIPE_FORMAT_DXT5_RGBA, BC3_UNORM},
- {PIPE_FORMAT_ETC1_RGB8, (SWR_FORMAT)-1},
+ {PIPE_FORMAT_DXT1_SRGBA, BC1_UNORM_SRGB},
+ {PIPE_FORMAT_DXT3_SRGBA, BC2_UNORM_SRGB},
+ {PIPE_FORMAT_DXT5_SRGBA, BC3_UNORM_SRGB},
- {PIPE_FORMAT_R8G8_R8B8_UNORM, (SWR_FORMAT)-1},
- {PIPE_FORMAT_G8R8_B8R8_UNORM, (SWR_FORMAT)-1},
+ {PIPE_FORMAT_RGTC1_UNORM, BC4_UNORM},
+ {PIPE_FORMAT_RGTC1_SNORM, BC4_SNORM},
+ {PIPE_FORMAT_RGTC2_UNORM, BC5_UNORM},
+ {PIPE_FORMAT_RGTC2_SNORM, BC5_SNORM},
- {PIPE_FORMAT_R8G8B8X8_SNORM, (SWR_FORMAT)-1},
- {PIPE_FORMAT_R8G8B8X8_SRGB, (SWR_FORMAT)-1},
- {PIPE_FORMAT_R8G8B8X8_UINT, (SWR_FORMAT)-1},
- {PIPE_FORMAT_R8G8B8X8_SINT, (SWR_FORMAT)-1},
- {PIPE_FORMAT_B10G10R10X2_UNORM, B10G10R10X2_UNORM},
- {PIPE_FORMAT_R16G16B16X16_UNORM, R16G16B16X16_UNORM},
- {PIPE_FORMAT_R16G16B16X16_SNORM, (SWR_FORMAT)-1},
- {PIPE_FORMAT_R16G16B16X16_FLOAT, R16G16B16X16_FLOAT},
- {PIPE_FORMAT_R16G16B16X16_UINT, (SWR_FORMAT)-1},
- {PIPE_FORMAT_R16G16B16X16_SINT, (SWR_FORMAT)-1},
- {PIPE_FORMAT_R32G32B32X32_FLOAT, R32G32B32X32_FLOAT},
- {PIPE_FORMAT_R32G32B32X32_UINT, (SWR_FORMAT)-1},
- {PIPE_FORMAT_R32G32B32X32_SINT, (SWR_FORMAT)-1},
-
- {PIPE_FORMAT_R8A8_SNORM, (SWR_FORMAT)-1},
- {PIPE_FORMAT_R16A16_UNORM, (SWR_FORMAT)-1},
- {PIPE_FORMAT_R16A16_SNORM, (SWR_FORMAT)-1},
- {PIPE_FORMAT_R16A16_FLOAT, (SWR_FORMAT)-1},
- {PIPE_FORMAT_R32A32_FLOAT, (SWR_FORMAT)-1},
- {PIPE_FORMAT_R8A8_UINT, (SWR_FORMAT)-1},
- {PIPE_FORMAT_R8A8_SINT, (SWR_FORMAT)-1},
- {PIPE_FORMAT_R16A16_UINT, (SWR_FORMAT)-1},
- {PIPE_FORMAT_R16A16_SINT, (SWR_FORMAT)-1},
- {PIPE_FORMAT_R32A32_UINT, (SWR_FORMAT)-1},
- {PIPE_FORMAT_R32A32_SINT, (SWR_FORMAT)-1},
- {PIPE_FORMAT_R10G10B10A2_UINT, R10G10B10A2_UINT},
+ {PIPE_FORMAT_L16A16_UNORM, L16A16_UNORM},
+ {PIPE_FORMAT_I16_UNORM, I16_UNORM},
+ {PIPE_FORMAT_L16_FLOAT, L16_FLOAT},
+ {PIPE_FORMAT_L16A16_FLOAT, L16A16_FLOAT},
+ {PIPE_FORMAT_I16_FLOAT, I16_FLOAT},
+ {PIPE_FORMAT_L32_FLOAT, L32_FLOAT},
+ {PIPE_FORMAT_L32A32_FLOAT, L32A32_FLOAT},
+ {PIPE_FORMAT_I32_FLOAT, I32_FLOAT},
- {PIPE_FORMAT_B5G6R5_SRGB, B5G6R5_UNORM_SRGB}
- };
+ {PIPE_FORMAT_I8_UINT, I8_UINT},
+ {PIPE_FORMAT_L8_UINT, L8_UINT},
+ {PIPE_FORMAT_L8A8_UINT, L8A8_UINT},
- try {
- return mesa2swr.at(format);
- }
- catch (std::out_of_range) {
- debug_printf("asked to convert unsupported format %s\n",
- util_format_name(format));
+ {PIPE_FORMAT_I8_SINT, I8_SINT},
+ {PIPE_FORMAT_L8_SINT, L8_SINT},
+ {PIPE_FORMAT_L8A8_SINT, L8A8_SINT},
+
+ */
+ };
+ auto it = mesa2swr.find(format);
+ if (it == mesa2swr.end())
return (SWR_FORMAT)-1;
- }
+ else
+ return it->second;
}
static boolean
struct sw_winsys *winsys = screen->winsys;
struct sw_displaytarget *dt;
+ const unsigned width = align(res->swr.width, res->swr.halign);
+ const unsigned height = align(res->swr.height, res->swr.valign);
+
UINT stride;
dt = winsys->displaytarget_create(winsys,
res->base.bind,
res->base.format,
- res->alignedWidth,
- res->alignedHeight,
+ width, height,
64, NULL,
&stride);
/* Clear the display target surface */
if (map)
- memset(map, 0, res->alignedHeight * stride);
+ memset(map, 0, height * stride);
winsys->displaytarget_unmap(winsys, dt);
return TRUE;
}
-static boolean
+static bool
swr_texture_layout(struct swr_screen *screen,
struct swr_resource *res,
boolean allocate)
if (res->has_stencil && !res->has_depth)
fmt = PIPE_FORMAT_R8_UINT;
+ /* We always use the SWR layout. For 2D and 3D textures this looks like:
+ *
+ * |<------- pitch ------->|
+ * +=======================+-------
+ * |Array 0 | ^
+ * | | |
+ * | Level 0 | |
+ * | | |
+ * | | qpitch
+ * +-----------+-----------+ |
+ * | | L2L2L2L2 | |
+ * | Level 1 | L3L3 | |
+ * | | L4 | v
+ * +===========+===========+-------
+ * |Array 1 |
+ * | |
+ * | Level 0 |
+ * | |
+ * | |
+ * +-----------+-----------+
+ * | | L2L2L2L2 |
+ * | Level 1 | L3L3 |
+ * | | L4 |
+ * +===========+===========+
+ *
+ * The overall width in bytes is known as the pitch, while the overall
+ * height in rows is the qpitch. Array slices are laid out logically below
+ * one another, qpitch rows apart. For 3D surfaces, the "level" values are
+ * just invalid for the higher array numbers (since depth is also
+ * minified). 1D and 1D array surfaces are stored effectively the same way,
+ * except that pitch never plays into it. All the levels are logically
+ * adjacent to each other on the X axis. The qpitch becomes the number of
+ * elements between array slices, while the pitch is unused.
+ *
+ * Each level's sizes are subject to the valign and halign settings of the
+ * surface. For compressed formats that swr is unaware of, we will use an
+ * appropriately-sized uncompressed format, and scale the widths/heights.
+ *
+ * This surface is stored inside res->swr. For depth/stencil textures,
+ * res->secondary will have an identically-laid-out but R8_UINT-formatted
+ * stencil tree. In the Z32F_S8 case, the primary surface still has 64-bpp
+ * texels, to simplify map/unmap logic which copies the stencil values
+ * in/out.
+ */
+
res->swr.width = pt->width0;
res->swr.height = pt->height0;
- res->swr.depth = pt->depth0;
res->swr.type = swr_convert_target_type(pt->target);
res->swr.tileMode = SWR_TILE_NONE;
res->swr.format = mesa_to_swr_format(fmt);
- res->swr.numSamples = (1 << pt->nr_samples);
-
- SWR_FORMAT_INFO finfo = GetFormatInfo(res->swr.format);
+ res->swr.numSamples = std::max(1u, pt->nr_samples);
- size_t total_size = 0;
- unsigned width = pt->width0;
- unsigned height = pt->height0;
- unsigned depth = pt->depth0;
- unsigned layers = pt->array_size;
-
- for (int level = 0; level <= pt->last_level; level++) {
- unsigned alignedWidth, alignedHeight;
- unsigned num_slices;
+ if (pt->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) {
+ res->swr.halign = KNOB_MACROTILE_X_DIM;
+ res->swr.valign = KNOB_MACROTILE_Y_DIM;
+ } else {
+ res->swr.halign = 1;
+ res->swr.valign = 1;
+ }
- if (pt->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) {
- alignedWidth = align(width, KNOB_MACROTILE_X_DIM);
- alignedHeight = align(height, KNOB_MACROTILE_Y_DIM);
- } else {
- alignedWidth = width;
- alignedHeight = height;
+ unsigned halign = res->swr.halign * util_format_get_blockwidth(fmt);
+ unsigned width = align(pt->width0, halign);
+ if (pt->target == PIPE_TEXTURE_1D || pt->target == PIPE_TEXTURE_1D_ARRAY) {
+ for (int level = 1; level <= pt->last_level; level++)
+ width += align(u_minify(pt->width0, level), halign);
+ res->swr.pitch = util_format_get_blocksize(fmt);
+ res->swr.qpitch = util_format_get_nblocksx(fmt, width);
+ } else {
+ // The pitch is the overall width of the texture in bytes. Most of the
+ // time this is the pitch of level 0 since all the other levels fit
+ // underneath it. However in some degenerate situations, the width of
+ // level1 + level2 may be larger. In that case, we use those
+ // widths. This can happen if, e.g. halign is 32, and the width of level
+ // 0 is 32 or less. In that case, the aligned levels 1 and 2 will also
+ // be 32 each, adding up to 64.
+ unsigned valign = res->swr.valign * util_format_get_blockheight(fmt);
+ if (pt->last_level > 1) {
+ width = std::max<uint32_t>(
+ width,
+ align(u_minify(pt->width0, 1), halign) +
+ align(u_minify(pt->width0, 2), halign));
}
-
- if (level == 0) {
- res->alignedWidth = alignedWidth;
- res->alignedHeight = alignedHeight;
+ res->swr.pitch = util_format_get_stride(fmt, width);
+
+ // The qpitch is controlled by either the height of the second LOD, or
+ // the combination of all the later LODs.
+ unsigned height = align(pt->height0, valign);
+ if (pt->last_level == 1) {
+ height += align(u_minify(pt->height0, 1), valign);
+ } else if (pt->last_level > 1) {
+ unsigned level1 = align(u_minify(pt->height0, 1), valign);
+ unsigned level2 = 0;
+ for (int level = 2; level <= pt->last_level; level++) {
+ level2 += align(u_minify(pt->height0, level), valign);
+ }
+ height += std::max(level1, level2);
}
+ res->swr.qpitch = util_format_get_nblocksy(fmt, height);
+ }
- res->row_stride[level] = alignedWidth * finfo.Bpp;
- res->img_stride[level] = res->row_stride[level] * alignedHeight;
- res->mip_offsets[level] = total_size;
-
- if (pt->target == PIPE_TEXTURE_3D)
- num_slices = depth;
- else if (pt->target == PIPE_TEXTURE_1D_ARRAY
- || pt->target == PIPE_TEXTURE_2D_ARRAY
- || pt->target == PIPE_TEXTURE_CUBE
- || pt->target == PIPE_TEXTURE_CUBE_ARRAY)
- num_slices = layers;
- else
- num_slices = 1;
-
- total_size += res->img_stride[level] * num_slices;
- if (total_size > SWR_MAX_TEXTURE_SIZE)
- return FALSE;
+ if (pt->target == PIPE_TEXTURE_3D)
+ res->swr.depth = pt->depth0;
+ else
+ res->swr.depth = pt->array_size;
+
+ // Fix up swr format if necessary so that LOD offset computation works
+ if (res->swr.format == (SWR_FORMAT)-1) {
+ switch (util_format_get_blocksize(fmt)) {
+ default:
+ unreachable("Unexpected format block size");
+ case 1: res->swr.format = R8_UINT; break;
+ case 2: res->swr.format = R16_UINT; break;
+ case 4: res->swr.format = R32_UINT; break;
+ case 8:
+ if (util_format_is_compressed(fmt))
+ res->swr.format = BC4_UNORM;
+ else
+ res->swr.format = R32G32_UINT;
+ break;
+ case 16:
+ if (util_format_is_compressed(fmt))
+ res->swr.format = BC5_UNORM;
+ else
+ res->swr.format = R32G32B32A32_UINT;
+ break;
+ }
+ }
- width = u_minify(width, 1);
- height = u_minify(height, 1);
- depth = u_minify(depth, 1);
+ for (int level = 0; level <= pt->last_level; level++) {
+ res->mip_offsets[level] =
+ ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->swr);
}
- res->swr.halign = res->alignedWidth;
- res->swr.valign = res->alignedHeight;
- res->swr.pitch = res->row_stride[0];
+ size_t total_size =
+ (size_t)res->swr.depth * res->swr.qpitch * res->swr.pitch;
+ if (total_size > SWR_MAX_TEXTURE_SIZE)
+ return false;
if (allocate) {
res->swr.pBaseAddress = (uint8_t *)AlignedMalloc(total_size, 64);
if (res->has_depth && res->has_stencil) {
- SWR_FORMAT_INFO finfo = GetFormatInfo(res->secondary.format);
- res->secondary.width = pt->width0;
- res->secondary.height = pt->height0;
- res->secondary.depth = pt->depth0;
- res->secondary.type = SURFACE_2D;
- res->secondary.tileMode = SWR_TILE_NONE;
+ res->secondary = res->swr;
res->secondary.format = R8_UINT;
- res->secondary.numSamples = (1 << pt->nr_samples);
- res->secondary.pitch = res->alignedWidth * finfo.Bpp;
+ res->secondary.pitch = res->swr.pitch / util_format_get_blocksize(fmt);
+
+ for (int level = 0; level <= pt->last_level; level++) {
+ res->secondary_mip_offsets[level] =
+ ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->secondary);
+ }
res->secondary.pBaseAddress = (uint8_t *)AlignedMalloc(
- res->alignedHeight * res->secondary.pitch, 64);
+ res->secondary.depth * res->secondary.qpitch *
+ res->secondary.pitch, 64);
}
}
- return TRUE;
+ return true;
}
static boolean
PUBLIC
struct pipe_screen *
-swr_create_screen(struct sw_winsys *winsys)
+swr_create_screen_internal(struct sw_winsys *winsys)
{
struct swr_screen *screen = CALLOC_STRUCT(swr_screen);
return &screen->base;
}
-struct sw_winsys *
-swr_get_winsys(struct pipe_screen *pipe)
-{
- return ((struct swr_screen *)pipe)->winsys;
-}
-
-struct sw_displaytarget *
-swr_get_displaytarget(struct pipe_resource *resource)
-{
- return ((struct swr_resource *)resource)->display_target;
-}