#pragma pop_macro("DEBUG")
#include "state.h"
-#include "state_llvm.h"
+#include "gen_state_llvm.h"
#include "builder.h"
#include "tgsi/tgsi_strings.h"
#include "gallivm/lp_bld_tgsi.h"
#include "swr_context.h"
-#include "swr_context_llvm.h"
+#include "gen_swr_context_llvm.h"
#include "swr_resource.h"
#include "swr_state.h"
#include "swr_screen.h"
sizeof(key.vs_output_semantic_idx));
swr_generate_sampler_key(swr_fs->info, ctx, PIPE_SHADER_FRAGMENT, key);
+
+ key.poly_stipple_enable = ctx->rasterizer->poly_stipple_enable &&
+ ctx->poly_stipple.prim_is_poly;
}
void
gallivm_free_ir(gallivm);
}
+ void WriteVS(Value *pVal, Value *pVsContext, Value *pVtxOutput,
+ unsigned slot, unsigned channel);
+
struct gallivm_state *gallivm;
PFN_VERTEX_FUNC CompileVS(struct swr_context *ctx, swr_jit_vs_key &key);
PFN_PIXEL_KERNEL CompileFS(struct swr_context *ctx, swr_jit_fs_key &key);
IRB()->SetInsertPoint(unwrap(LLVMGetInsertBlock(gallivm->builder)));
+#if USE_SIMD16_FRONTEND
+ const uint32_t simdVertexStride = sizeof(simdvertex) * 2;
+ const uint32_t numSimdBatches = (pGS->maxNumVerts + (mVWidth * 2) - 1) / (mVWidth * 2);
+#else
const uint32_t simdVertexStride = sizeof(simdvertex);
- const uint32_t numSimdBatches = (pGS->maxNumVerts + 7) / 8;
+ const uint32_t numSimdBatches = (pGS->maxNumVerts + mVWidth - 1) / mVWidth;
+#endif
const uint32_t inputPrimStride = numSimdBatches * simdVertexStride;
Value *pStream = LOAD(iface->pGsCtx, { 0, SWR_GS_CONTEXT_pStream });
inputPrimStride * 6,
inputPrimStride * 7 } );
- Value *vVertexSlot = ASHR(unwrap(emitted_vertices_vec), 3);
- Value *vSimdSlot = AND(unwrap(emitted_vertices_vec), 7);
+#if USE_SIMD16_FRONTEND
+ const uint32_t simdShift = log2(mVWidth * 2);
+ Value *vSimdSlot = AND(unwrap(emitted_vertices_vec), (mVWidth * 2) - 1);
+#else
+ const uint32_t simdShift = log2(mVWidth);
+ Value *vSimdSlot = AND(unwrap(emitted_vertices_vec), mVWidth - 1);
+#endif
+ Value *vVertexSlot = ASHR(unwrap(emitted_vertices_vec), simdShift);
for (uint32_t attrib = 0; attrib < iface->num_outputs; ++attrib) {
uint32_t attribSlot = attrib;
attribSlot = VERTEX_POINT_SIZE_SLOT;
else if (iface->info->output_semantic_name[attrib] == TGSI_SEMANTIC_PRIMID)
attribSlot = VERTEX_PRIMID_SLOT;
+ else if (iface->info->output_semantic_name[attrib] == TGSI_SEMANTIC_LAYER)
+ attribSlot = VERTEX_RTAI_SLOT;
+#if USE_SIMD16_FRONTEND
+ Value *vOffsetsAttrib =
+ ADD(vOffsets, MUL(vVertexSlot, VIMMED1((uint32_t)sizeof(simdvertex) * 2)));
+ vOffsetsAttrib =
+ ADD(vOffsetsAttrib, VIMMED1((uint32_t)(attribSlot*sizeof(simdvector) * 2)));
+#else
Value *vOffsetsAttrib =
ADD(vOffsets, MUL(vVertexSlot, VIMMED1((uint32_t)sizeof(simdvertex))));
vOffsetsAttrib =
ADD(vOffsetsAttrib, VIMMED1((uint32_t)(attribSlot*sizeof(simdvector))));
+#endif
vOffsetsAttrib =
ADD(vOffsetsAttrib, MUL(vSimdSlot, VIMMED1((uint32_t)sizeof(float))));
MASKED_SCATTER(vData, vPtrs, 32, vMask1);
+#if USE_SIMD16_FRONTEND
+ vOffsetsAttrib =
+ ADD(vOffsetsAttrib, VIMMED1((uint32_t)sizeof(simdscalar) * 2));
+#else
vOffsetsAttrib =
ADD(vOffsetsAttrib, VIMMED1((uint32_t)sizeof(simdscalar)));
+#endif
}
}
}
LLVMValueRef emitted_prims_vec)
{
swr_gs_llvm_iface *iface = (swr_gs_llvm_iface*)gs_base;
- SWR_GS_STATE *pGS = iface->pGsState;
IRB()->SetInsertPoint(unwrap(LLVMGetInsertBlock(gallivm->builder)));
AttrBuilder attrBuilder;
attrBuilder.addStackAlignmentAttr(JM()->mVWidth * sizeof(float));
- AttributeSet attrSet = AttributeSet::get(
- JM()->mContext, AttributeSet::FunctionIndex, attrBuilder);
std::vector<Type *> gsArgs{PointerType::get(Gen_swr_draw_context(JM()), 0),
PointerType::get(Gen_SWR_GS_CONTEXT(JM()), 0)};
GlobalValue::ExternalLinkage,
"GS",
JM()->mpCurrentModule);
+#if HAVE_LLVM < 0x0500
+ AttributeSet attrSet = AttributeSet::get(
+ JM()->mContext, AttributeSet::FunctionIndex, attrBuilder);
pFunction->addAttributes(AttributeSet::FunctionIndex, attrSet);
+#else
+ pFunction->addAttributes(AttributeList::FunctionIndex, attrBuilder);
+#endif
BasicBlock *block = BasicBlock::Create(JM()->mContext, "entry", pFunction);
IRB()->SetInsertPoint(block);
return func;
}
+void
+BuilderSWR::WriteVS(Value *pVal, Value *pVsContext, Value *pVtxOutput, unsigned slot, unsigned channel)
+{
+#if USE_SIMD16_FRONTEND
+ // interleave the simdvertex components into the dest simd16vertex
+ // slot16offset = slot8offset * 2
+ // comp16offset = comp8offset * 2 + alternateOffset
+
+ Value *offset = LOAD(pVsContext, { 0, SWR_VS_CONTEXT_AlternateOffset });
+ Value *pOut = GEP(pVtxOutput, { C(0), C(0), C(slot * 2), offset } );
+ STORE(pVal, pOut, {channel * 2});
+#else
+ Value *pOut = GEP(pVtxOutput, {0, 0, slot});
+ STORE(pVal, pOut, {0, channel});
+#endif
+}
+
PFN_VERTEX_FUNC
BuilderSWR::CompileVS(struct swr_context *ctx, swr_jit_vs_key &key)
{
AttrBuilder attrBuilder;
attrBuilder.addStackAlignmentAttr(JM()->mVWidth * sizeof(float));
- AttributeSet attrSet = AttributeSet::get(
- JM()->mContext, AttributeSet::FunctionIndex, attrBuilder);
std::vector<Type *> vsArgs{PointerType::get(Gen_swr_draw_context(JM()), 0),
PointerType::get(Gen_SWR_VS_CONTEXT(JM()), 0)};
GlobalValue::ExternalLinkage,
"VS",
JM()->mpCurrentModule);
+#if HAVE_LLVM < 0x0500
+ AttributeSet attrSet = AttributeSet::get(
+ JM()->mContext, AttributeSet::FunctionIndex, attrBuilder);
pFunction->addAttributes(AttributeSet::FunctionIndex, attrSet);
+#else
+ pFunction->addAttributes(AttributeList::FunctionIndex, attrBuilder);
+#endif
BasicBlock *block = BasicBlock::Create(JM()->mContext, "entry", pFunction);
IRB()->SetInsertPoint(block);
uint32_t outSlot = attrib;
if (swr_vs->info.base.output_semantic_name[attrib] == TGSI_SEMANTIC_PSIZE)
outSlot = VERTEX_POINT_SIZE_SLOT;
- STORE(val, vtxOutput, {0, 0, outSlot, channel});
+ WriteVS(val, pVsCtx, vtxOutput, outSlot, channel);
}
}
&swr_vs->info.base);
if (val < 4) {
LLVMValueRef dist = LLVMBuildLoad(gallivm->builder, outputs[cv][val], "");
- STORE(unwrap(dist), vtxOutput, {0, 0, VERTEX_CLIPCULL_DIST_LO_SLOT, val});
+ WriteVS(unwrap(dist), pVsCtx, vtxOutput, VERTEX_CLIPCULL_DIST_LO_SLOT, val);
} else {
LLVMValueRef dist = LLVMBuildLoad(gallivm->builder, outputs[cv][val - 4], "");
- STORE(unwrap(dist), vtxOutput, {0, 0, VERTEX_CLIPCULL_DIST_HI_SLOT, val - 4});
+ WriteVS(unwrap(dist), pVsCtx, vtxOutput, VERTEX_CLIPCULL_DIST_HI_SLOT, val - 4);
}
continue;
}
FMUL(unwrap(cw), VBROADCAST(pw)))));
if (val < 4)
- STORE(dist, vtxOutput, {0, 0, VERTEX_CLIPCULL_DIST_LO_SLOT, val});
+ WriteVS(dist, pVsCtx, vtxOutput, VERTEX_CLIPCULL_DIST_LO_SLOT, val);
else
- STORE(dist, vtxOutput, {0, 0, VERTEX_CLIPCULL_DIST_HI_SLOT, val - 4});
+ WriteVS(dist, pVsCtx, vtxOutput, VERTEX_CLIPCULL_DIST_HI_SLOT, val - 4);
}
}
AttrBuilder attrBuilder;
attrBuilder.addStackAlignmentAttr(JM()->mVWidth * sizeof(float));
- AttributeSet attrSet = AttributeSet::get(
- JM()->mContext, AttributeSet::FunctionIndex, attrBuilder);
std::vector<Type *> fsArgs{PointerType::get(Gen_swr_draw_context(JM()), 0),
PointerType::get(Gen_SWR_PS_CONTEXT(JM()), 0)};
GlobalValue::ExternalLinkage,
"FS",
JM()->mpCurrentModule);
+#if HAVE_LLVM < 0x0500
+ AttributeSet attrSet = AttributeSet::get(
+ JM()->mContext, AttributeSet::FunctionIndex, attrBuilder);
pFunction->addAttributes(AttributeSet::FunctionIndex, attrSet);
+#else
+ pFunction->addAttributes(AttributeList::FunctionIndex, attrBuilder);
+#endif
BasicBlock *block = BasicBlock::Create(JM()->mContext, "entry", pFunction);
IRB()->SetInsertPoint(block);
memset(&system_values, 0, sizeof(system_values));
struct lp_build_mask_context mask;
+ bool uses_mask = false;
- if (swr_fs->info.base.uses_kill) {
- Value *mask_val = LOAD(pPS, {0, SWR_PS_CONTEXT_activeMask}, "activeMask");
+ if (swr_fs->info.base.uses_kill ||
+ key.poly_stipple_enable) {
+ Value *vActiveMask = NULL;
+ if (swr_fs->info.base.uses_kill) {
+ vActiveMask = LOAD(pPS, {0, SWR_PS_CONTEXT_activeMask}, "activeMask");
+ }
+ if (key.poly_stipple_enable) {
+ // first get fragment xy coords and clip to stipple bounds
+ Value *vXf = LOAD(pPS, {0, SWR_PS_CONTEXT_vX, PixelPositions_UL});
+ Value *vYf = LOAD(pPS, {0, SWR_PS_CONTEXT_vY, PixelPositions_UL});
+ Value *vXu = FP_TO_UI(vXf, mSimdInt32Ty);
+ Value *vYu = FP_TO_UI(vYf, mSimdInt32Ty);
+
+ // stipple pattern is 32x32, which means that one line of stipple
+ // is stored in one word:
+ // vXstipple is bit offset inside 32-bit stipple word
+ // vYstipple is word index is stipple array
+ Value *vXstipple = AND(vXu, VIMMED1(0x1f)); // & (32-1)
+ Value *vYstipple = AND(vYu, VIMMED1(0x1f)); // & (32-1)
+
+ // grab stipple pattern base address
+ Value *stipplePtr = GEP(hPrivateData, {0, swr_draw_context_polyStipple, 0});
+ stipplePtr = BITCAST(stipplePtr, mInt8PtrTy);
+
+ // peform a gather to grab stipple words for each lane
+ Value *vStipple = GATHERDD(VUNDEF_I(), stipplePtr, vYstipple,
+ VIMMED1(0xffffffff), C((char)4));
+
+ // create a mask with one bit corresponding to the x stipple
+ // and AND it with the pattern, to see if we have a bit
+ Value *vBitMask = LSHR(VIMMED1(0x80000000), vXstipple);
+ Value *vStippleMask = AND(vStipple, vBitMask);
+ vStippleMask = ICMP_NE(vStippleMask, VIMMED1(0));
+ vStippleMask = VMASK(vStippleMask);
+
+ if (swr_fs->info.base.uses_kill) {
+ vActiveMask = AND(vActiveMask, vStippleMask);
+ } else {
+ vActiveMask = vStippleMask;
+ }
+ }
lp_build_mask_begin(
- &mask, gallivm, lp_type_float_vec(32, 32 * 8), wrap(mask_val));
+ &mask, gallivm, lp_type_float_vec(32, 32 * 8), wrap(vActiveMask));
+ uses_mask = true;
}
lp_build_tgsi_soa(gallivm,
swr_fs->pipe.tokens,
lp_type_float_vec(32, 32 * 8),
- swr_fs->info.base.uses_kill ? &mask : NULL, // mask
+ uses_mask ? &mask : NULL, // mask
wrap(consts_ptr),
wrap(const_sizes_ptr),
&system_values,
}
LLVMValueRef mask_result = 0;
- if (swr_fs->info.base.uses_kill) {
+ if (uses_mask) {
mask_result = lp_build_mask_end(&mask);
}
IRB()->SetInsertPoint(unwrap(LLVMGetInsertBlock(gallivm->builder)));
- if (swr_fs->info.base.uses_kill) {
+ if (uses_mask) {
STORE(unwrap(mask_result), pPS, {0, SWR_PS_CONTEXT_activeMask});
}
projects / mesa.git / blobdiff