load.input_image_format = V3D_OUTPUT_IMAGE_FORMAT_S8;
else
load.input_image_format = surf->format;
+ load.r_b_swap = surf->swap_rb;
if (surf->tiling == VC5_TILING_UIF_NO_XOR ||
surf->tiling == VC5_TILING_UIF_XOR) {
else
store.output_image_format = surf->format;
+ store.r_b_swap = surf->swap_rb;
store.memory_format = surf->tiling;
if (surf->tiling == VC5_TILING_UIF_NO_XOR ||
assert(buffer != ZSTENCIL);
store.raw_mode = true;
if (!last_store) {
- store.disable_colour_buffers_clear_on_write = true;
+ store.disable_color_buffers_clear_on_write = true;
store.disable_z_buffer_clear_on_write = true;
store.disable_stencil_buffer_clear_on_write = true;
} else {
- store.disable_colour_buffers_clear_on_write =
+ store.disable_color_buffers_clear_on_write =
!(((pipe_bit & PIPE_CLEAR_COLOR_BUFFERS) &&
general_color_clear &&
(job->clear & pipe_bit)));
{
uint32_t loads_pending = job->load;
- for (int i = 0; i < VC5_MAX_DRAW_BUFFERS; i++) {
+ for (int i = 0; i < V3D_MAX_DRAW_BUFFERS; i++) {
uint32_t bit = PIPE_CLEAR_COLOR0 << i;
if (!(loads_pending & bit))
continue;
* tile coordinates.
*/
if (loads_pending) {
- cl_emit(cl, RELOAD_TILE_COLOUR_BUFFER, load) {
- load.disable_colour_buffer_load =
+ cl_emit(cl, RELOAD_TILE_COLOR_BUFFER, load) {
+ load.disable_color_buffer_load =
(~loads_pending &
PIPE_CLEAR_COLOR_BUFFERS) >>
PIPE_FIRST_COLOR_BUFFER_BIT;
v3d_rcl_emit_stores(struct v3d_job *job, struct v3d_cl *cl)
{
#if V3D_VERSION < 40
- MAYBE_UNUSED bool needs_color_clear = job->clear & PIPE_CLEAR_COLOR_BUFFERS;
- MAYBE_UNUSED bool needs_z_clear = job->clear & PIPE_CLEAR_DEPTH;
- MAYBE_UNUSED bool needs_s_clear = job->clear & PIPE_CLEAR_STENCIL;
+ UNUSED bool needs_color_clear = job->clear & PIPE_CLEAR_COLOR_BUFFERS;
+ UNUSED bool needs_z_clear = job->clear & PIPE_CLEAR_DEPTH;
+ UNUSED bool needs_s_clear = job->clear & PIPE_CLEAR_STENCIL;
/* For clearing color in a TLB general on V3D 3.3:
*
* perspective. Non-MSAA surfaces will use
* STORE_MULTI_SAMPLE_RESOLVED_TILE_COLOR_BUFFER_EXTENDED.
*/
- for (int i = 0; i < VC5_MAX_DRAW_BUFFERS; i++) {
+ for (int i = 0; i < V3D_MAX_DRAW_BUFFERS; i++) {
uint32_t bit = PIPE_CLEAR_COLOR0 << i;
if (!(job->store & bit))
continue;
/* Note that when set this will clear all of the color
* buffers.
*/
- store.disable_colour_buffers_clear_on_write =
+ store.disable_color_buffers_clear_on_write =
!needs_color_clear;
store.disable_z_buffer_clear_on_write =
!needs_z_clear;
}
}
#else /* V3D_VERSION >= 40 */
+ /* If we're emitting an RCL with GL_ARB_framebuffer_no_attachments,
+ * we still need to emit some sort of store.
+ */
+ if (!job->store) {
+ cl_emit(cl, STORE_TILE_BUFFER_GENERAL, store) {
+ store.buffer_to_store = NONE;
+ }
+ }
+
assert(!stores_pending);
/* GFXH-1461/GFXH-1689: The per-buffer store command's clear
/* The binner starts out writing tiles assuming that the initial mode
* is triangles, so make sure that's the case.
*/
- cl_emit(cl, PRIMITIVE_LIST_FORMAT, fmt) {
+ cl_emit(cl, PRIM_LIST_FORMAT, fmt) {
fmt.primitive_type = LIST_TRIANGLES;
}
v3d_emit_z_stencil_config(struct v3d_job *job, struct v3d_surface *surf,
struct v3d_resource *rsc, bool is_separate_stencil)
{
- cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_Z_STENCIL_CONFIG, zs) {
+ cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_Z_STENCIL, zs) {
zs.address = cl_address(rsc->bo, surf->offset);
if (!is_separate_stencil) {
v3d_job_add_bo(job, job->rcl.bo);
int nr_cbufs = 0;
- for (int i = 0; i < VC5_MAX_DRAW_BUFFERS; i++) {
+ for (int i = 0; i < V3D_MAX_DRAW_BUFFERS; i++) {
if (job->cbufs[i])
nr_cbufs = i + 1;
}
- /* Comon config must be the first TILE_RENDERING_MODE_CONFIGURATION
+ /* Comon config must be the first TILE_RENDERING_MODE_CFG
* and Z_STENCIL_CLEAR_VALUES must be last. The ones in between are
* optional updates to the previous HW state.
*/
- cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_COMMON_CONFIGURATION,
- config) {
+ cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_COMMON, config) {
#if V3D_VERSION < 40
config.enable_z_store = job->store & PIPE_CLEAR_DEPTH;
config.enable_stencil_store = job->store & PIPE_CLEAR_STENCIL;
struct v3d_surface *surf = v3d_surface(psurf);
struct v3d_resource *rsc = v3d_resource(psurf->texture);
- MAYBE_UNUSED uint32_t config_pad = 0;
+ UNUSED uint32_t config_pad = 0;
uint32_t clear_pad = 0;
/* XXX: Set the pad for raster. */
}
#if V3D_VERSION < 40
- cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_RENDER_TARGET_CONFIG, rt) {
+ cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_COLOR, rt) {
rt.address = cl_address(rsc->bo, surf->offset);
rt.internal_type = surf->internal_type;
rt.output_image_format = surf->format;
}
#endif /* V3D_VERSION < 40 */
- cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_CLEAR_COLORS_PART1,
+ cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_CLEAR_COLORS_PART1,
clear) {
clear.clear_color_low_32_bits = job->clear_color[i][0];
clear.clear_color_next_24_bits = job->clear_color[i][1] & 0xffffff;
};
if (surf->internal_bpp >= V3D_INTERNAL_BPP_64) {
- cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_CLEAR_COLORS_PART2,
+ cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_CLEAR_COLORS_PART2,
clear) {
clear.clear_color_mid_low_32_bits =
((job->clear_color[i][1] >> 24) |
}
if (surf->internal_bpp >= V3D_INTERNAL_BPP_128 || clear_pad) {
- cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_CLEAR_COLORS_PART3,
+ cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_CLEAR_COLORS_PART3,
clear) {
clear.uif_padded_height_in_uif_blocks = clear_pad;
clear.clear_color_high_16_bits = job->clear_color[i][3] >> 16;
}
#if V3D_VERSION >= 40
- cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_RENDER_TARGET_CONFIG, rt) {
+ cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_COLOR, rt) {
v3d_setup_render_target(job, 0,
&rt.render_target_0_internal_bpp,
&rt.render_target_0_internal_type,
#endif /* V3D_VERSION < 40 */
/* Ends rendering mode config. */
- cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_Z_STENCIL_CLEAR_VALUES,
+ cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_ZS_CLEAR_VALUES,
clear) {
clear.z_clear_value = job->clear_z;
clear.stencil_clear_value = job->clear_s;
list.address = cl_address(job->tile_alloc, 0);
}
- cl_emit(&job->rcl, MULTICORE_RENDERING_SUPERTILE_CONFIGURATION, config) {
+ cl_emit(&job->rcl, MULTICORE_RENDERING_SUPERTILE_CFG, config) {
uint32_t frame_w_in_supertiles, frame_h_in_supertiles;
const uint32_t max_supertiles = 256;
v3d_rcl_emit_generic_per_tile_list(job, nr_cbufs - 1);
- /* XXX: Use Morton order */
+ /* XXX perf: We should expose GL_MESA_tile_raster_order to improve X11
+ * performance, but we should use Morton order otherwise to improve
+ * cache locality.
+ */
uint32_t supertile_w_in_pixels = job->tile_width * supertile_w;
uint32_t supertile_h_in_pixels = job->tile_height * supertile_h;
uint32_t min_x_supertile = job->draw_min_x / supertile_w_in_pixels;
}
}
+ if (job->tmu_dirty_rcl) {
+ cl_emit(&job->rcl, L1_CACHE_FLUSH_CONTROL, flush) {
+ flush.tmu_config_cache_clear = 0xf;
+ flush.tmu_data_cache_clear = 0xf;
+ flush.uniforms_cache_clear = 0xf;
+ flush.instruction_cache_clear = 0xf;
+ }
+
+ cl_emit(&job->rcl, L2T_CACHE_FLUSH_CONTROL, flush) {
+ flush.l2t_flush_mode = L2T_FLUSH_MODE_CLEAN;
+ flush.l2t_flush_start = cl_address(NULL, 0);
+ flush.l2t_flush_end = cl_address(NULL, ~0);
+ }
+ }
+
cl_emit(&job->rcl, END_OF_RENDERING, end);
}
projects / mesa.git / blobdiff