gallium: split transfer_inline_write into buffer and texture callbacks

[mesa.git] / src / gallium / drivers / vc4 / kernel / vc4_drv.h

diff --git a/src/gallium/drivers/vc4/kernel/vc4_drv.h b/src/gallium/drivers/vc4/kernel/vc4_drv.h
index 1fd8aa9fb28d5ff9551233ddf91ca8ac3d059774..90f45397d83110fa21324544bd63e442388e2d2f 100644 (file)
--- a/src/gallium/drivers/vc4/kernel/vc4_drv.h
+++ b/src/gallium/drivers/vc4/kernel/vc4_drv.h
@@ -26,17 +26,6 @@
 
 #include "vc4_simulator_validate.h"
 
-enum vc4_bo_mode {
-       VC4_MODE_UNDECIDED,
-       VC4_MODE_RENDER,
-       VC4_MODE_SHADER,
-};
-
-struct vc4_bo_exec_state {
-       struct drm_gem_cma_object *bo;
-       enum vc4_bo_mode mode;
-};
-
 struct vc4_exec_info {
        /* Sequence number for this bin/render job. */
        uint64_t seqno;
@@ -47,7 +36,7 @@ struct vc4_exec_info {
        /* This is the array of BOs that were looked up at the start of exec.
         * Command validation will use indices into this array.
         */
-       struct vc4_bo_exec_state *bo;
+       struct drm_gem_cma_object **bo;
        uint32_t bo_count;
 
        /* List of other BOs used in the job that need to be released
@@ -72,7 +61,6 @@ struct vc4_exec_info {
         * command lists.
         */
        struct vc4_shader_state {
-               uint8_t packet;
                uint32_t addr;
                /* Maximum vertex index referenced by any primitive using this
                 * shader state.
@@ -88,10 +76,13 @@ struct vc4_exec_info {
        bool found_tile_binning_mode_config_packet;
        bool found_start_tile_binning_packet;
        bool found_increment_semaphore_packet;
+       bool found_flush;
        uint8_t bin_tiles_x, bin_tiles_y;
        struct drm_gem_cma_object *tile_bo;
        uint32_t tile_alloc_offset;
 
+       uint32_t tile_width, tile_height;
+
        /**
         * Computed addresses pointing into exec_bo where we start the
         * bin thread (ct0) and render thread (ct1).
@@ -99,6 +90,9 @@ struct vc4_exec_info {
        uint32_t ct0ca, ct0ea;
        uint32_t ct1ca, ct1ea;
 
+       /* Pointer to the unvalidated bin CL (if present). */
+       void *bin_u;
+
        /* Pointers to the shader recs.  These paddr gets incremented as CL
         * packets are relocated in validate_gl_shader_state, and the vaddrs
         * (u and v) get incremented and size decremented as the shader recs
@@ -153,6 +147,9 @@ struct vc4_validated_shader_info
        uint32_t uniforms_src_size;
        uint32_t num_texture_samples;
        struct vc4_texture_sample_info *texture_samples;
+
+       uint32_t num_uniform_addr_offsets;
+       uint32_t *uniform_addr_offsets;
 };
 
 /* vc4_validate.c */
@@ -168,10 +165,8 @@ vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec);
 struct vc4_validated_shader_info *
 vc4_validate_shader(struct drm_gem_cma_object *shader_obj);
 
-bool vc4_use_bo(struct vc4_exec_info *exec,
-               uint32_t hindex,
-               enum vc4_bo_mode mode,
-               struct drm_gem_cma_object **obj);
+struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec,
+                                     uint32_t hindex);
 
 int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec);