gallium: split transfer_inline_write into buffer and texture callbacks

[mesa.git] / src / gallium / drivers / vc4 / kernel / vc4_drv.h

diff --git a/src/gallium/drivers/vc4/kernel/vc4_drv.h b/src/gallium/drivers/vc4/kernel/vc4_drv.h
index 81ffa03a6fa01d21b2ffffcb4a4b2486c2ca7868..90f45397d83110fa21324544bd63e442388e2d2f 100644 (file)
--- a/src/gallium/drivers/vc4/kernel/vc4_drv.h
+++ b/src/gallium/drivers/vc4/kernel/vc4_drv.h
@@ -26,29 +26,24 @@
 
 #include "vc4_simulator_validate.h"
 
-enum vc4_bo_mode {
-       VC4_MODE_UNDECIDED,
-       VC4_MODE_TILE_ALLOC,
-       VC4_MODE_TSDA,
-       VC4_MODE_RENDER,
-       VC4_MODE_SHADER,
-};
-
-struct vc4_bo_exec_state {
-       struct drm_gem_cma_object *bo;
-       enum vc4_bo_mode mode;
-};
+struct vc4_exec_info {
+       /* Sequence number for this bin/render job. */
+       uint64_t seqno;
 
-struct exec_info {
        /* Kernel-space copy of the ioctl arguments */
        struct drm_vc4_submit_cl *args;
 
        /* This is the array of BOs that were looked up at the start of exec.
         * Command validation will use indices into this array.
         */
-       struct vc4_bo_exec_state *bo;
+       struct drm_gem_cma_object **bo;
        uint32_t bo_count;
 
+       /* List of other BOs used in the job that need to be released
+        * once the job is complete.
+        */
+       struct list_head unref_list;
+
        /* Current unvalidated indices into @bo loaded by the non-hardware
         * VC4_PACKET_GEM_HANDLES.
         */
@@ -66,7 +61,6 @@ struct exec_info {
         * command lists.
         */
        struct vc4_shader_state {
-               uint8_t packet;
                uint32_t addr;
                /* Maximum vertex index referenced by any primitive using this
                 * shader state.
@@ -80,14 +74,14 @@ struct exec_info {
        uint32_t shader_state_count;
 
        bool found_tile_binning_mode_config_packet;
-       bool found_tile_rendering_mode_config_packet;
        bool found_start_tile_binning_packet;
        bool found_increment_semaphore_packet;
-       bool found_wait_on_semaphore_packet;
+       bool found_flush;
        uint8_t bin_tiles_x, bin_tiles_y;
-       uint32_t fb_width, fb_height;
-       uint32_t tile_alloc_init_block_size;
-       struct drm_gem_cma_object *tile_alloc_bo;
+       struct drm_gem_cma_object *tile_bo;
+       uint32_t tile_alloc_offset;
+
+       uint32_t tile_width, tile_height;
 
        /**
         * Computed addresses pointing into exec_bo where we start the
@@ -96,6 +90,9 @@ struct exec_info {
        uint32_t ct0ca, ct0ea;
        uint32_t ct1ca, ct1ea;
 
+       /* Pointer to the unvalidated bin CL (if present). */
+       void *bin_u;
+
        /* Pointers to the shader recs.  These paddr gets incremented as CL
         * packets are relocated in validate_gl_shader_state, and the vaddrs
         * (u and v) get incremented and size decremented as the shader recs
@@ -150,22 +147,32 @@ struct vc4_validated_shader_info
        uint32_t uniforms_src_size;
        uint32_t num_texture_samples;
        struct vc4_texture_sample_info *texture_samples;
+
+       uint32_t num_uniform_addr_offsets;
+       uint32_t *uniform_addr_offsets;
 };
 
 /* vc4_validate.c */
 int
-vc4_validate_cl(struct drm_device *dev,
-                void *validated,
-                void *unvalidated,
-                uint32_t len,
-                bool is_bin,
-                struct exec_info *exec);
+vc4_validate_bin_cl(struct drm_device *dev,
+                   void *validated,
+                   void *unvalidated,
+                   struct vc4_exec_info *exec);
 
 int
-vc4_validate_shader_recs(struct drm_device *dev, struct exec_info *exec);
+vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec);
 
 struct vc4_validated_shader_info *
-vc4_validate_shader(struct drm_gem_cma_object *shader_obj,
-                    uint32_t start_offset);
+vc4_validate_shader(struct drm_gem_cma_object *shader_obj);
+
+struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec,
+                                     uint32_t hindex);
+
+int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec);
+
+bool vc4_check_tex_size(struct vc4_exec_info *exec,
+                       struct drm_gem_cma_object *fbo,
+                       uint32_t offset, uint8_t tiling_format,
+                       uint32_t width, uint32_t height, uint8_t cpp);
 
 #endif /* VC4_DRV_H */