return pctx->create_surface(pctx, prsc, &tmpl);
}
+static bool
+is_tile_unaligned(unsigned size, unsigned tile_size)
+{
+ return size & (tile_size - 1);
+}
+
static bool
vc4_tile_blit(struct pipe_context *pctx, const struct pipe_blit_info *info)
{
struct vc4_context *vc4 = vc4_context(pctx);
+ bool old_msaa = vc4->msaa;
+ int old_tile_width = vc4->tile_width;
+ int old_tile_height = vc4->tile_height;
+ bool msaa = (info->src.resource->nr_samples > 1 ||
+ info->dst.resource->nr_samples > 1);
+ int tile_width = msaa ? 32 : 64;
+ int tile_height = msaa ? 32 : 64;
if (util_format_is_depth_or_stencil(info->dst.resource->format))
return false;
+ if (info->scissor_enable)
+ return false;
+
if ((info->mask & PIPE_MASK_RGBA) == 0)
return false;
- if (info->dst.box.x != 0 || info->dst.box.y != 0 ||
- info->src.box.x != 0 || info->src.box.y != 0 ||
+ if (info->dst.box.x != info->src.box.x ||
+ info->dst.box.y != info->src.box.y ||
info->dst.box.width != info->src.box.width ||
info->dst.box.height != info->src.box.height) {
return false;
}
+ int dst_surface_width = u_minify(info->dst.resource->width0,
+ info->dst.level);
+ int dst_surface_height = u_minify(info->dst.resource->height0,
+ info->dst.level);
+ if (is_tile_unaligned(info->dst.box.x, tile_width) ||
+ is_tile_unaligned(info->dst.box.y, tile_height) ||
+ (is_tile_unaligned(info->dst.box.width, tile_width) &&
+ info->dst.box.x + info->dst.box.width != dst_surface_width) ||
+ (is_tile_unaligned(info->dst.box.height, tile_height) &&
+ info->dst.box.y + info->dst.box.height != dst_surface_height)) {
+ return false;
+ }
+
+ /* VC4_PACKET_LOAD_TILE_BUFFER_GENERAL uses the
+ * VC4_PACKET_TILE_RENDERING_MODE_CONFIG's width (determined by our
+ * destination surface) to determine the stride. This may be wrong
+ * when reading from texture miplevels > 0, which are stored in
+ * POT-sized areas. For MSAA, the tile addresses are computed
+ * explicitly by the RCL, but still use the destination width to
+ * determine the stride (which could be fixed by explicitly supplying
+ * it in the ABI).
+ */
+ struct vc4_resource *rsc = vc4_resource(info->src.resource);
+
+ uint32_t stride;
+
+ if (info->src.resource->nr_samples > 1)
+ stride = align(dst_surface_width, 32) * 4 * rsc->cpp;
+ else if (rsc->slices[info->src.level].tiling == VC4_TILING_FORMAT_T)
+ stride = align(dst_surface_width * rsc->cpp, 128);
+ else
+ stride = align(dst_surface_width * rsc->cpp, 16);
+
+ if (stride != rsc->slices[info->src.level].stride)
+ return false;
+
if (info->dst.resource->format != info->src.resource->format)
return false;
vc4_flush(pctx);
+ if (false) {
+ fprintf(stderr, "RCL blit from %d,%d to %d,%d (%d,%d)\n",
+ info->src.box.x,
+ info->src.box.y,
+ info->dst.box.x,
+ info->dst.box.y,
+ info->dst.box.width,
+ info->dst.box.height);
+ }
+
struct pipe_surface *dst_surf =
vc4_get_blit_surface(pctx, info->dst.resource, info->dst.level);
struct pipe_surface *src_surf =
vc4_get_blit_surface(pctx, info->src.resource, info->src.level);
pipe_surface_reference(&vc4->color_read, src_surf);
- pipe_surface_reference(&vc4->color_write, dst_surf);
+ pipe_surface_reference(&vc4->color_write,
+ dst_surf->texture->nr_samples > 1 ?
+ NULL : dst_surf);
+ pipe_surface_reference(&vc4->msaa_color_write,
+ dst_surf->texture->nr_samples > 1 ?
+ dst_surf : NULL);
pipe_surface_reference(&vc4->zs_read, NULL);
pipe_surface_reference(&vc4->zs_write, NULL);
- vc4->draw_min_x = 0;
- vc4->draw_min_y = 0;
- vc4->draw_max_x = dst_surf->width;
- vc4->draw_max_y = dst_surf->height;
+ pipe_surface_reference(&vc4->msaa_zs_write, NULL);
+
+ vc4->draw_min_x = info->dst.box.x;
+ vc4->draw_min_y = info->dst.box.y;
+ vc4->draw_max_x = info->dst.box.x + info->dst.box.width;
+ vc4->draw_max_y = info->dst.box.y + info->dst.box.height;
vc4->draw_width = dst_surf->width;
vc4->draw_height = dst_surf->height;
+
+ vc4->tile_width = tile_width;
+ vc4->tile_height = tile_height;
+ vc4->msaa = msaa;
vc4->needs_flush = true;
+
vc4_job_submit(vc4);
+ vc4->msaa = old_msaa;
+ vc4->tile_width = old_tile_width;
+ vc4->tile_height = old_tile_height;
+
pipe_surface_reference(&dst_surf, NULL);
pipe_surface_reference(&src_surf, NULL);
struct vc4_context *vc4 = vc4_context(ctx);
if (!util_blitter_is_blit_supported(vc4->blitter, info)) {
- fprintf(stderr, "blit unsupported %s -> %s",
+ fprintf(stderr, "blit unsupported %s -> %s\n",
util_format_short_name(info->src.resource->format),
util_format_short_name(info->dst.resource->format));
return false;
{
struct pipe_blit_info info = *blit_info;
- if (info.src.resource->nr_samples > 1 &&
- info.dst.resource->nr_samples <= 1 &&
- !util_format_is_depth_or_stencil(info.src.resource->format) &&
- !util_format_is_pure_integer(info.src.resource->format)) {
- fprintf(stderr, "color resolve unimplemented");
- return;
- }
-
if (vc4_tile_blit(pctx, blit_info))
return;
}
if (info.mask & PIPE_MASK_S) {
- fprintf(stderr, "cannot blit stencil, skipping");
+ fprintf(stderr, "cannot blit stencil, skipping\n");
info.mask &= ~PIPE_MASK_S;
}