* IN THE SOFTWARE.
*/
+#include "util/u_prim.h"
#include "util/u_format.h"
#include "util/u_pack_color.h"
#include "indices/u_primconvert.h"
#include "vc4_context.h"
#include "vc4_resource.h"
+static void
+vc4_get_draw_cl_space(struct vc4_context *vc4)
+{
+ /* Binner gets our packet state -- vc4_emit.c contents,
+ * and the primitive itself.
+ */
+ cl_ensure_space(&vc4->bcl, 256);
+
+ /* Nothing for rcl -- that's covered by vc4_context.c */
+
+ /* shader_rec gets up to 12 dwords of reloc handles plus a maximally
+ * sized shader_rec (104 bytes base for 8 vattrs plus 32 bytes of
+ * vattr stride).
+ */
+ cl_ensure_space(&vc4->shader_rec, 12 * sizeof(uint32_t) + 104 + 8 * 32);
+
+ /* Uniforms are covered by vc4_write_uniforms(). */
+
+ /* There could be up to 16 textures per stage, plus misc other
+ * pointers.
+ */
+ cl_ensure_space(&vc4->bo_handles, (2 * 16 + 20) * sizeof(uint32_t));
+ cl_ensure_space(&vc4->bo_pointers,
+ (2 * 16 + 20) * sizeof(struct vc4_bo *));
+}
+
/**
* Does the initial bining command list setup for drawing to a given FBO.
*/
if (vc4->needs_flush)
return;
+ vc4_get_draw_cl_space(vc4);
+
uint32_t width = vc4->framebuffer.width;
uint32_t height = vc4->framebuffer.height;
uint32_t tilew = align(width, 64) / 64;
* BO allocations align to that anyway), then for some reason the
* simulator wants an extra page available, even if you have overflow
* memory set up.
+ *
+ * XXX: The binner only does 28-bit addressing math, so the tile alloc
+ * and tile state should be in the same BO and that BO needs to not
+ * cross a 256MB boundary, somehow.
*/
uint32_t tile_alloc_size = 32 * tilew * tileh;
tile_alloc_size = align(tile_alloc_size, 4096);
util_primconvert_save_index_buffer(vc4->primconvert, &vc4->indexbuf);
util_primconvert_save_rasterizer_state(vc4->primconvert, &vc4->rasterizer->base);
util_primconvert_draw_vbo(vc4->primconvert, info);
+ perf_debug("Fallback conversion for %d %s vertices\n",
+ info->count, u_prim_name(info->mode));
return;
}
+ vc4_get_draw_cl_space(vc4);
+
struct vc4_vertex_stateobj *vtx = vc4->vtx;
struct vc4_vertexbuf_stateobj *vertexbuf = &vc4->vertexbuf;
cl_u32(&vc4->shader_rec, 0); /* UBO offset written by kernel */
cl_u16(&vc4->shader_rec, 0); /* vs num uniforms */
- cl_u8(&vc4->shader_rec, (1 << num_elements_emit) - 1); /* vs attribute array bitfield */
- cl_u8(&vc4->shader_rec, 16 * num_elements_emit); /* vs total attribute size */
+ cl_u8(&vc4->shader_rec, vc4->prog.vs->vattrs_live);
+ cl_u8(&vc4->shader_rec, vc4->prog.vs->vattr_offsets[8]);
cl_reloc(vc4, &vc4->shader_rec, vc4->prog.vs->bo, 0);
cl_u32(&vc4->shader_rec, 0); /* UBO offset written by kernel */
cl_u16(&vc4->shader_rec, 0); /* cs num uniforms */
- cl_u8(&vc4->shader_rec, (1 << num_elements_emit) - 1); /* cs attribute array bitfield */
- cl_u8(&vc4->shader_rec, 16 * num_elements_emit); /* cs total attribute size */
+ cl_u8(&vc4->shader_rec, vc4->prog.cs->vattrs_live);
+ cl_u8(&vc4->shader_rec, vc4->prog.cs->vattr_offsets[8]);
cl_reloc(vc4, &vc4->shader_rec, vc4->prog.cs->bo, 0);
cl_u32(&vc4->shader_rec, 0); /* UBO offset written by kernel */
uint32_t max_index = 0xffff;
+ uint32_t vpm_offset = 0;
for (int i = 0; i < vtx->num_elements; i++) {
struct pipe_vertex_element *elem = &vtx->pipe[i];
struct pipe_vertex_buffer *vb =
cl_reloc(vc4, &vc4->shader_rec, rsc->bo, offset);
cl_u8(&vc4->shader_rec, elem_size - 1);
cl_u8(&vc4->shader_rec, vb->stride);
- cl_u8(&vc4->shader_rec, i * 16); /* VS VPM offset */
- cl_u8(&vc4->shader_rec, i * 16); /* CS VPM offset */
+ cl_u8(&vc4->shader_rec, vc4->prog.vs->vattr_offsets[i]);
+ cl_u8(&vc4->shader_rec, vc4->prog.cs->vattr_offsets[i]);
+
+ vpm_offset += align(elem_size, 4);
if (vb->stride > 0) {
max_index = MIN2(max_index,
*/
if (info->indexed) {
struct vc4_resource *rsc = vc4_resource(vc4->indexbuf.buffer);
-
- assert(vc4->indexbuf.index_size == 1 ||
- vc4->indexbuf.index_size == 2);
+ uint32_t offset = vc4->indexbuf.offset;
+ uint32_t index_size = vc4->indexbuf.index_size;
+ if (rsc->shadow_parent) {
+ vc4_update_shadow_index_buffer(pctx, &vc4->indexbuf);
+ offset = 0;
+ }
cl_start_reloc(&vc4->bcl, 1);
cl_u8(&vc4->bcl, VC4_PACKET_GL_INDEXED_PRIMITIVE);
cl_u8(&vc4->bcl,
info->mode |
- (vc4->indexbuf.index_size == 2 ?
+ (index_size == 2 ?
VC4_INDEX_BUFFER_U16:
VC4_INDEX_BUFFER_U8));
cl_u32(&vc4->bcl, info->count);
- cl_reloc(vc4, &vc4->bcl, rsc->bo, vc4->indexbuf.offset);
+ cl_reloc(vc4, &vc4->bcl, rsc->bo, offset);
cl_u32(&vc4->bcl, max_index);
} else {
cl_u8(&vc4->bcl, VC4_PACKET_GL_ARRAY_PRIMITIVE);
{
union util_color uc;
util_pack_color(rgba, format, &uc);
- return uc.ui[0];
+ if (util_format_get_blocksize(format) == 2)
+ return uc.us;
+ else
+ return uc.ui[0];
}
static void
/* We can't flag new buffers for clearing once we've queued draws. We
* could avoid this by using the 3d engine to clear.
*/
- if (vc4->draw_call_queued)
+ if (vc4->draw_call_queued) {
+ perf_debug("Flushing rendering to process new clear.");
vc4_flush(pctx);
+ }
if (buffers & PIPE_CLEAR_COLOR0) {
vc4->clear_color[0] = vc4->clear_color[1] =
if (buffers & PIPE_CLEAR_STENCIL)
vc4->clear_stencil = stencil;
+ vc4->draw_min_x = 0;
+ vc4->draw_min_y = 0;
+ vc4->draw_max_x = vc4->framebuffer.width;
+ vc4->draw_max_y = vc4->framebuffer.height;
vc4->cleared |= buffers;
vc4->resolve |= buffers;
projects / mesa.git / blobdiff