struct vc4_context *vc4 = vc4_context(pctx);
struct vc4_cl_out *bcl = cl_start(&vc4->bcl);
- if (vc4->dirty & (VC4_DIRTY_SCISSOR | VC4_DIRTY_VIEWPORT)) {
+ if (vc4->dirty & (VC4_DIRTY_SCISSOR | VC4_DIRTY_VIEWPORT |
+ VC4_DIRTY_RASTERIZER)) {
float *vpscale = vc4->viewport.scale;
float *vptranslate = vc4->viewport.translate;
float vp_minx = -fabsf(vpscale[0]) + vptranslate[0];
float vp_maxx = fabsf(vpscale[0]) + vptranslate[0];
float vp_miny = -fabsf(vpscale[1]) + vptranslate[1];
float vp_maxy = fabsf(vpscale[1]) + vptranslate[1];
- uint32_t minx = MAX2(vc4->scissor.minx, vp_minx);
- uint32_t miny = MAX2(vc4->scissor.miny, vp_miny);
- uint32_t maxx = MIN2(vc4->scissor.maxx, vp_maxx);
- uint32_t maxy = MIN2(vc4->scissor.maxy, vp_maxy);
+
+ /* Clip to the scissor if it's enabled, but still clip to the
+ * drawable regardless since that controls where the binner
+ * tries to put things.
+ *
+ * Additionally, always clip the rendering to the viewport,
+ * since the hardware does guardband clipping, meaning
+ * primitives would rasterize outside of the view volume.
+ */
+ uint32_t minx, miny, maxx, maxy;
+ if (!vc4->rasterizer->base.scissor) {
+ minx = MAX2(vp_minx, 0);
+ miny = MAX2(vp_miny, 0);
+ maxx = MIN2(vp_maxx, vc4->draw_width);
+ maxy = MIN2(vp_maxy, vc4->draw_height);
+ } else {
+ minx = MAX2(vp_minx, vc4->scissor.minx);
+ miny = MAX2(vp_miny, vc4->scissor.miny);
+ maxx = MIN2(vp_maxx, vc4->scissor.maxx);
+ maxy = MIN2(vp_maxy, vc4->scissor.maxy);
+ }
cl_u8(&bcl, VC4_PACKET_CLIP_WINDOW);
cl_u16(&bcl, minx);
}
if (vc4->dirty & (VC4_DIRTY_RASTERIZER | VC4_DIRTY_ZSA)) {
+ uint8_t ez_enable_mask_out = ~0;
+
+ /* HW-2905: If the RCL ends up doing a full-res load when
+ * multisampling, then early Z tracking may end up with values
+ * from the previous tile due to a HW bug. Disable it to
+ * avoid that.
+ *
+ * We should be able to skip this when the Z is cleared, but I
+ * was seeing bad rendering on glxgears -samples 4 even in
+ * that case.
+ */
+ if (vc4->msaa)
+ ez_enable_mask_out &= ~VC4_CONFIG_BITS_EARLY_Z;
+
cl_u8(&bcl, VC4_PACKET_CONFIGURATION_BITS);
cl_u8(&bcl,
vc4->rasterizer->config_bits[0] |
vc4->rasterizer->config_bits[1] |
vc4->zsa->config_bits[1]);
cl_u8(&bcl,
- vc4->rasterizer->config_bits[2] |
- vc4->zsa->config_bits[2]);
+ (vc4->rasterizer->config_bits[2] |
+ vc4->zsa->config_bits[2]) & ez_enable_mask_out);
}
if (vc4->dirty & VC4_DIRTY_RASTERIZER) {