radeonsi: use a compiler queue with a low priority for optimized shaders

[mesa.git] / src / gallium / drivers / vc4 / vc4_nir_lower_blend.c

diff --git a/src/gallium/drivers/vc4/vc4_nir_lower_blend.c b/src/gallium/drivers/vc4/vc4_nir_lower_blend.c
index 56f6c3bd0e9533a56bc9ffc570b2fe5050886133..a28ebb5bb7c784200b522e2c3c9907ba621365e4 100644 (file)
--- a/src/gallium/drivers/vc4/vc4_nir_lower_blend.c
+++ b/src/gallium/drivers/vc4/vc4_nir_lower_blend.c
@@ -494,7 +494,7 @@ vc4_nir_emit_alpha_test_discard(struct vc4_compile *c, nir_builder *b,
         discard->num_components = 1;
         discard->src[0] = nir_src_for_ssa(nir_inot(b, condition));
         nir_builder_instr_insert(b, &discard->instr);
-        c->s->info->fs.uses_discard = true;
+        c->s->info.fs.uses_discard = true;
 }
 
 static nir_ssa_def *
@@ -637,7 +637,7 @@ vc4_nir_lower_blend_instr(struct vc4_compile *c, nir_builder *b,
                  * coordinate, instead.
                  */
                 nir_ssa_def *num_samples = nir_imm_float(b, VC4_MAX_SAMPLES);
-                nir_ssa_def *num_bits = nir_f2i(b, nir_fmul(b, a, num_samples));
+                nir_ssa_def *num_bits = nir_f2i32(b, nir_fmul(b, a, num_samples));
                 nir_ssa_def *bitmask = nir_isub(b,
                                                 nir_ishl(b,
                                                          nir_imm_int(b, 1),