vc4: Add support for texture rectangles
[mesa.git] / src / gallium / drivers / vc4 / vc4_qir.h
index 5332478039aa8f760be863a428f86eb0362b125b..1b450cac8c5171f31128038a5e5b84c4584a1c93 100644 (file)
@@ -59,6 +59,7 @@ enum qop {
         QOP_CMP,
 
         QOP_FTOI,
+        QOP_ITOF,
         QOP_RCP,
         QOP_RSQ,
         QOP_EXP2,
@@ -71,6 +72,24 @@ enum qop {
         QOP_VPM_READ,
         QOP_TLB_COLOR_WRITE,
         QOP_VARY_ADD_C,
+
+        /** Texture x coordinate parameter write */
+        QOP_TEX_S,
+        /** Texture y coordinate parameter write */
+        QOP_TEX_T,
+        /** Texture border color parameter or cube map z coordinate write */
+        QOP_TEX_R,
+        /** Texture LOD bias parameter write */
+        QOP_TEX_B,
+        /**
+         * Signal of texture read being necessary and then reading r4 into
+         * the destination
+         */
+        QOP_TEX_RESULT,
+        QOP_R4_UNPACK_A,
+        QOP_R4_UNPACK_B,
+        QOP_R4_UNPACK_C,
+        QOP_R4_UNPACK_D
 };
 
 struct simple_node {
@@ -119,6 +138,28 @@ enum quniform_contents {
         QUNIFORM_VIEWPORT_X_SCALE,
         QUNIFORM_VIEWPORT_Y_SCALE,
         /** @} */
+
+        /**
+         * A reference to a texture config parameter 0 uniform.
+         *
+         * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
+         * defines texture type, miplevels, and such.  It will be found as a
+         * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
+         */
+        QUNIFORM_TEXTURE_CONFIG_P0,
+
+        /**
+         * A reference to a texture config parameter 1 uniform.
+         *
+         * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
+         * defines texture width, height, filters, and wrap modes.  It will be
+         * found as a parameter to the second QOP_TEX_[STRB] instruction in a
+         * sequence.
+         */
+        QUNIFORM_TEXTURE_CONFIG_P1,
+
+        QUNIFORM_TEXRECT_SCALE_X,
+        QUNIFORM_TEXRECT_SCALE_Y,
 };
 
 struct qcompile {
@@ -132,6 +173,7 @@ struct qcompile {
         uint64_t *qpu_insts;
         uint32_t qpu_inst_count;
         uint32_t qpu_inst_size;
+        uint32_t num_inputs;
 };
 
 struct qcompile *qir_compile_init(void);
@@ -176,6 +218,20 @@ qir_##name(struct qcompile *c, struct qreg a, struct qreg b)             \
         return t;                                                        \
 }
 
+#define QIR_NODST_1(name)                                               \
+static inline void                                                      \
+qir_##name(struct qcompile *c, struct qreg a)                           \
+{                                                                       \
+        qir_emit(c, qir_inst(QOP_##name, c->undef, a, c->undef));       \
+}
+
+#define QIR_NODST_2(name)                                               \
+static inline void                                                      \
+qir_##name(struct qcompile *c, struct qreg a, struct qreg b)            \
+{                                                                       \
+        qir_emit(c, qir_inst(QOP_##name, c->undef, a, b));       \
+}
+
 QIR_ALU1(MOV)
 QIR_ALU2(FADD)
 QIR_ALU2(FSUB)
@@ -185,17 +241,25 @@ QIR_ALU2(FMAX)
 QIR_ALU2(FMINABS)
 QIR_ALU2(FMAXABS)
 QIR_ALU1(FTOI)
+QIR_ALU1(ITOF)
 QIR_ALU1(RCP)
 QIR_ALU1(RSQ)
 QIR_ALU1(EXP2)
 QIR_ALU1(LOG2)
 QIR_ALU2(PACK_SCALED)
 QIR_ALU1(VARY_ADD_C)
+QIR_NODST_1(VPM_WRITE)
+QIR_NODST_2(TEX_S)
+QIR_NODST_2(TEX_T)
+QIR_NODST_2(TEX_R)
+QIR_NODST_2(TEX_B)
 
-static inline void
-qir_VPM_WRITE(struct qcompile *c, struct qreg a)
+static inline struct qreg
+qir_CMP(struct qcompile *c, struct qreg cmp, struct qreg a, struct qreg b)
 {
-        qir_emit(c, qir_inst(QOP_VPM_WRITE, c->undef, a, c->undef));
+        struct qreg t = qir_get_temp(c);
+        qir_emit(c, qir_inst4(QOP_CMP, t, cmp, a, b, c->undef));
+        return t;
 }
 
 #endif /* VC4_QIR_H */