virgl: Set meta data for textures from handle.
[mesa.git] / src / gallium / drivers / vc4 / vc4_qir.h
index a8f90cfe7af29c7422343c99f269fc42daf70e55..4d8bf60cf4401193924a18155c6a71503fb55ec3 100644 (file)
@@ -123,6 +123,7 @@ enum qop {
         QOP_SHR,
         QOP_ASR,
         QOP_MIN,
+        QOP_MIN_NOIMM,
         QOP_MAX,
         QOP_AND,
         QOP_OR,
@@ -268,7 +269,8 @@ enum quniform_contents {
 
         QUNIFORM_TEXTURE_MSAA_ADDR,
 
-        QUNIFORM_UBO_ADDR,
+        QUNIFORM_UBO0_ADDR,
+        QUNIFORM_UBO1_ADDR,
 
         QUNIFORM_TEXRECT_SCALE_X,
         QUNIFORM_TEXRECT_SCALE_Y,
@@ -298,31 +300,6 @@ struct vc4_varying_slot {
         uint8_t swizzle;
 };
 
-struct vc4_compiler_ubo_range {
-        /**
-         * offset in bytes from the start of the ubo where this range is
-         * uploaded.
-         *
-         * Only set once used is set.
-         */
-        uint32_t dst_offset;
-
-        /**
-         * offset in bytes from the start of the gallium uniforms where the
-         * data comes from.
-         */
-        uint32_t src_offset;
-
-        /** size in bytes of this ubo range */
-        uint32_t size;
-
-        /**
-         * Set if this range is used by the shader for indirect uniforms
-         * access.
-         */
-        bool used;
-};
-
 struct vc4_key {
         struct vc4_uncompiled_shader *shader_state;
         struct {
@@ -353,7 +330,6 @@ struct vc4_fs_key {
         bool stencil_full_writemasks;
         bool is_points;
         bool is_lines;
-        bool alpha_test;
         bool point_coord_upper_left;
         bool light_twoside;
         bool msaa;
@@ -363,6 +339,7 @@ struct vc4_fs_key {
         uint8_t alpha_test_func;
         uint8_t logicop_func;
         uint32_t point_sprite_mask;
+        uint32_t ubo_1_size;
 
         struct pipe_rt_blend_state blend;
 };
@@ -439,14 +416,6 @@ struct vc4_compile {
         uint32_t outputs_array_size;
         uint32_t uniforms_array_size;
 
-        struct vc4_compiler_ubo_range *ubo_ranges;
-        uint32_t ubo_ranges_array_size;
-        /** Number of uniform areas declared in ubo_ranges. */
-        uint32_t num_uniform_ranges;
-        /** Number of uniform areas used for indirect addressed loads. */
-        uint32_t num_ubo_ranges;
-        uint32_t next_ubo_dst_offset;
-
         /* State for whether we're executing on each channel currently.  0 if
          * yes, otherwise a block number + 1 that the channel jumped to.
          */
@@ -505,6 +474,7 @@ struct vc4_compile {
         struct qblock *cur_block;
         struct qblock *loop_cont_block;
         struct qblock *loop_break_block;
+        struct qblock *last_top_block;
 
         struct list_head qpu_inst_list;
 
@@ -577,6 +547,7 @@ int qir_get_tex_uniform_src(struct qinst *inst);
 bool qir_reg_equals(struct qreg a, struct qreg b);
 bool qir_has_side_effects(struct vc4_compile *c, struct qinst *inst);
 bool qir_has_side_effect_reads(struct vc4_compile *c, struct qinst *inst);
+bool qir_has_uniform_read(struct qinst *inst);
 bool qir_is_mul(struct qinst *inst);
 bool qir_is_raw_mov(struct qinst *inst);
 bool qir_is_tex(struct qinst *inst);
@@ -589,6 +560,8 @@ uint8_t qir_channels_written(struct qinst *inst);
 
 void qir_dump(struct vc4_compile *c);
 void qir_dump_inst(struct vc4_compile *c, struct qinst *inst);
+char *qir_describe_uniform(enum quniform_contents contents, uint32_t data,
+                           const uint32_t *uniforms);
 const char *qir_get_stage_name(enum qstage stage);
 
 void qir_validate(struct vc4_compile *c);
@@ -724,6 +697,7 @@ QIR_ALU2(SHL)
 QIR_ALU2(SHR)
 QIR_ALU2(ASR)
 QIR_ALU2(MIN)
+QIR_ALU2(MIN_NOIMM)
 QIR_ALU2(MAX)
 QIR_ALU2(AND)
 QIR_ALU2(OR)
@@ -887,6 +861,6 @@ qir_BRANCH(struct vc4_compile *c, uint8_t cond)
 
 #define qir_for_each_inst_inorder(inst, c)                              \
         qir_for_each_block(_block, c)                                   \
-                qir_for_each_inst(inst, _block)
+                qir_for_each_inst_safe(inst, _block)
 
 #endif /* VC4_QIR_H */