QPU_R_ELEM_QPU = 38,
QPU_R_NOP,
QPU_R_XY_PIXEL_COORD = 41,
- QPU_R_MS_REV_FLAGS = 41,
+ QPU_R_MS_REV_FLAGS = 42,
QPU_R_VPM = 48,
QPU_R_VPM_LD_BUSY,
QPU_R_VPM_LD_WAIT,
QPU_MUX_A,
QPU_MUX_B,
- /* non-hardware mux values */
- QPU_MUX_IMM,
+ /**
+ * Non-hardware mux value, stores a small immediate field to be
+ * programmed into raddr_b in the qpu_reg.index.
+ */
+ QPU_MUX_SMALL_IMM,
};
enum qpu_cond {
QPU_PACK_A_8D_SAT,
};
-enum qpu_unpack_r4 {
- QPU_UNPACK_R4_NOP,
- QPU_UNPACK_R4_F16A_TO_F32,
- QPU_UNPACK_R4_F16B_TO_F32,
- QPU_UNPACK_R4_8D_REP,
- QPU_UNPACK_R4_8A,
- QPU_UNPACK_R4_8B,
- QPU_UNPACK_R4_8C,
- QPU_UNPACK_R4_8D,
+enum qpu_unpack {
+ QPU_UNPACK_NOP,
+ QPU_UNPACK_16A,
+ QPU_UNPACK_16B,
+ QPU_UNPACK_8D_REP,
+ QPU_UNPACK_8A,
+ QPU_UNPACK_8B,
+ QPU_UNPACK_8C,
+ QPU_UNPACK_8D,
};
#define QPU_MASK(high, low) ((((uint64_t)1<<((high)-(low)+1))-1)<<(low))
#define QPU_GET_FIELD(word, field) ((uint32_t)(((word) & field ## _MASK) >> field ## _SHIFT))
+#define QPU_UPDATE_FIELD(inst, value, field) \
+ (((inst) & ~(field ## _MASK)) | QPU_SET_FIELD(value, field))
+
#define QPU_SIG_SHIFT 60
#define QPU_SIG_MASK QPU_MASK(63, 60)