gallium: Add a cap for offset_units_unscaled

[mesa.git] / src / gallium / drivers / vc4 / vc4_qpu_defines.h

diff --git a/src/gallium/drivers/vc4/vc4_qpu_defines.h b/src/gallium/drivers/vc4/vc4_qpu_defines.h
index 13c940c0f8e2a06a6b3ff499261f9f80e0a2d4f8..626dc3be6bed7f5c463e13383bb1547f4d75388e 100644 (file)
--- a/src/gallium/drivers/vc4/vc4_qpu_defines.h
+++ b/src/gallium/drivers/vc4/vc4_qpu_defines.h
@@ -25,8 +25,7 @@
 #define VC4_QPU_DEFINES_H
 
 #include <assert.h>
-
-#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
+#include <util/macros.h>
 
 enum qpu_op_add {
         QPU_A_NOP,
@@ -67,13 +66,14 @@ enum qpu_op_mul {
 };
 
 enum qpu_raddr {
+        QPU_R_FRAG_PAYLOAD_ZW = 15, /* W for A file, Z for B file */
         /* 0-31 are the plain regfile a or b fields */
         QPU_R_UNIF = 32,
         QPU_R_VARY = 35,
         QPU_R_ELEM_QPU = 38,
         QPU_R_NOP,
         QPU_R_XY_PIXEL_COORD = 41,
-        QPU_R_MS_REV_FLAGS = 41,
+        QPU_R_MS_REV_FLAGS = 42,
         QPU_R_VPM = 48,
         QPU_R_VPM_LD_BUSY,
         QPU_R_VPM_LD_WAIT,
@@ -147,8 +147,11 @@ enum qpu_mux {
         QPU_MUX_A,
         QPU_MUX_B,
 
-        /* non-hardware mux values */
-        QPU_MUX_IMM,
+        /**
+         * Non-hardware mux value, stores a small immediate field to be
+         * programmed into raddr_b in the qpu_reg.index.
+         */
+        QPU_MUX_SMALL_IMM,
 };
 
 enum qpu_cond {
@@ -195,6 +198,17 @@ enum qpu_pack_a {
         QPU_PACK_A_8D_SAT,
 };
 
+enum qpu_unpack {
+        QPU_UNPACK_NOP,
+        QPU_UNPACK_16A,
+        QPU_UNPACK_16B,
+        QPU_UNPACK_8D_REP,
+        QPU_UNPACK_8A,
+        QPU_UNPACK_8B,
+        QPU_UNPACK_8C,
+        QPU_UNPACK_8D,
+};
+
 #define QPU_MASK(high, low) ((((uint64_t)1<<((high)-(low)+1))-1)<<(low))
 /* Using the GNU statement expression extension */
 #define QPU_SET_FIELD(value, field)                                       \
@@ -206,9 +220,15 @@ enum qpu_pack_a {
 
 #define QPU_GET_FIELD(word, field) ((uint32_t)(((word)  & field ## _MASK) >> field ## _SHIFT))
 
+#define QPU_UPDATE_FIELD(inst, value, field)                              \
+        (((inst) & ~(field ## _MASK)) | QPU_SET_FIELD(value, field))
+
 #define QPU_SIG_SHIFT                   60
 #define QPU_SIG_MASK                    QPU_MASK(63, 60)
 
+#define QPU_UNPACK_SHIFT                57
+#define QPU_UNPACK_MASK                 QPU_MASK(59, 57)
+
 /**
  * If set, the pack field means PACK_MUL or R4 packing, instead of normal
  * regfile a packing.
@@ -223,6 +243,8 @@ enum qpu_pack_a {
 #define QPU_COND_MUL_SHIFT              46
 #define QPU_COND_MUL_MASK               QPU_MASK(48, 46)
 
+#define QPU_SF                          ((uint64_t)1 << 45)
+
 #define QPU_WADDR_ADD_SHIFT             38
 #define QPU_WADDR_ADD_MASK              QPU_MASK(43, 38)
 #define QPU_WADDR_MUL_SHIFT             32