freedreno/a4xx: format updates

[mesa.git] / src / gallium / drivers / vc4 / vc4_qpu_disasm.c

diff --git a/src/gallium/drivers/vc4/vc4_qpu_disasm.c b/src/gallium/drivers/vc4/vc4_qpu_disasm.c
index 4ec6d9657b7cac7955be36d0840ca01cab0c75d8..00aeb300a9b615f352c5e28275d8b37f6269d54d 100644 (file)
--- a/src/gallium/drivers/vc4/vc4_qpu_disasm.c
+++ b/src/gallium/drivers/vc4/vc4_qpu_disasm.c
@@ -93,6 +93,20 @@ static const char *qpu_pack_mul[] = {
         [QPU_PACK_MUL_8D] = "8d",
 };
 
+/* The QPU unpack for A and R4 files can be described the same, it's just that
+ * the R4 variants are convert-to-float only, with no int support.
+ */
+static const char *qpu_unpack[] = {
+        [QPU_UNPACK_NOP] = "",
+        [QPU_UNPACK_16A_TO_F32] = "16a",
+        [QPU_UNPACK_16B_TO_F32] = "16b",
+        [QPU_UNPACK_8D_REP] = "8d_rep",
+        [QPU_UNPACK_8A] = "8a",
+        [QPU_UNPACK_8B] = "8b",
+        [QPU_UNPACK_8C] = "8c",
+        [QPU_UNPACK_8D] = "8d",
+};
+
 static const char *special_read_a[] = {
         "uni",
         NULL,
@@ -211,7 +225,7 @@ static const char *qpu_condflags[] = {
 };
 
 #define DESC(array, index)                                        \
-        ((index > ARRAY_SIZE(array) || !(array)[index]) ?         \
+        ((index >= ARRAY_SIZE(array) || !(array)[index]) ?         \
          "???" : (array)[index])
 
 static const char *
@@ -263,6 +277,7 @@ print_alu_src(uint64_t inst, uint32_t mux)
         uint32_t raddr = (is_a ?
                           QPU_GET_FIELD(inst, QPU_RADDR_A) :
                           QPU_GET_FIELD(inst, QPU_RADDR_B));
+        uint32_t unpack = QPU_GET_FIELD(inst, QPU_UNPACK);
 
         if (mux <= QPU_MUX_R5)
                 fprintf(stderr, "r%d", mux);
@@ -276,9 +291,9 @@ print_alu_src(uint64_t inst, uint32_t mux)
                 else if (si <= 39)
                         fprintf(stderr, "%.1f", (float)(1 << (si - 32)));
                 else if (si <= 47)
-                        fprintf(stderr, "%f", 1.0f / (256 / (si - 39)));
+                        fprintf(stderr, "%f", 1.0f / (1 << (48 - si)));
                 else
-                        fprintf(stderr, "???");
+                        fprintf(stderr, "<bad imm %d>", si);
         } else if (raddr <= 31)
                 fprintf(stderr, "r%s%d", file, raddr);
         else {
@@ -287,6 +302,12 @@ print_alu_src(uint64_t inst, uint32_t mux)
                 else
                         fprintf(stderr, "%s", DESC(special_read_b, raddr - 32));
         }
+
+        if (unpack != QPU_UNPACK_NOP &&
+            ((mux == QPU_MUX_A && !(inst & QPU_PM)) ||
+             (mux == QPU_MUX_R4 && (inst & QPU_PM)))) {
+                fprintf(stderr, ".%s", DESC(qpu_unpack, unpack));
+        }
 }
 
 static void
@@ -369,7 +390,7 @@ vc4_qpu_disasm(const uint64_t *instructions, int num_instructions)
 
                 switch (sig) {
                 case QPU_SIG_BRANCH:
-                        fprintf(stderr, "branch\n");
+                        fprintf(stderr, "branch");
                         break;
                 case QPU_SIG_LOAD_IMM:
                         print_load_imm(inst);
@@ -380,10 +401,10 @@ vc4_qpu_disasm(const uint64_t *instructions, int num_instructions)
                         print_add_op(inst);
                         fprintf(stderr, " ; ");
                         print_mul_op(inst);
-
-                        if (num_instructions != 1)
-                                fprintf(stderr, "\n");
                         break;
                 }
+
+                if (num_instructions != 1)
+                        fprintf(stderr, "\n");
         }
 }