vc4: fix memory leak

[mesa.git] / src / gallium / drivers / vc4 / vc4_qpu_disasm.c

diff --git a/src/gallium/drivers/vc4/vc4_qpu_disasm.c b/src/gallium/drivers/vc4/vc4_qpu_disasm.c
index 2511fcfc937b69e568668f8893ca613984978647..d48e753df3d1d7726c17c67ad43a045d468501d5 100644 (file)
--- a/src/gallium/drivers/vc4/vc4_qpu_disasm.c
+++ b/src/gallium/drivers/vc4/vc4_qpu_disasm.c
@@ -98,8 +98,8 @@ static const char *qpu_pack_mul[] = {
  */
 static const char *qpu_unpack[] = {
         [QPU_UNPACK_NOP] = "",
-        [QPU_UNPACK_16A_TO_F32] = "16a",
-        [QPU_UNPACK_16B_TO_F32] = "16b",
+        [QPU_UNPACK_16A] = "16a",
+        [QPU_UNPACK_16B] = "16b",
         [QPU_UNPACK_8D_REP] = "8d_rep",
         [QPU_UNPACK_8A] = "8a",
         [QPU_UNPACK_8B] = "8b",
@@ -213,7 +213,7 @@ static const char *qpu_pack_a[] = {
         [QPU_PACK_A_8D_SAT] = ".8d.sat",
 };
 
-static const char *qpu_condflags[] = {
+static const char *qpu_cond[] = {
         [QPU_COND_NEVER] = ".never",
         [QPU_COND_ALWAYS] = "",
         [QPU_COND_ZS] = ".zs",
@@ -225,7 +225,7 @@ static const char *qpu_condflags[] = {
 };
 
 #define DESC(array, index)                                        \
-        ((index > ARRAY_SIZE(array) || !(array)[index]) ?         \
+        ((index >= ARRAY_SIZE(array) || !(array)[index]) ?         \
          "???" : (array)[index])
 
 static const char *
@@ -245,6 +245,31 @@ get_special_write_desc(int reg, bool is_a)
         return special_write[reg];
 }
 
+void
+vc4_qpu_disasm_pack_mul(FILE *out, uint32_t pack)
+{
+        fprintf(out, ".%s", DESC(qpu_pack_mul, pack));
+}
+
+void
+vc4_qpu_disasm_pack_a(FILE *out, uint32_t pack)
+{
+        fprintf(out, "%s", DESC(qpu_pack_a, pack));
+}
+
+void
+vc4_qpu_disasm_unpack(FILE *out, uint32_t unpack)
+{
+        if (unpack != QPU_UNPACK_NOP)
+                fprintf(out, ".%s", DESC(qpu_unpack, unpack));
+}
+
+void
+vc4_qpu_disasm_cond(FILE *out, uint32_t cond)
+{
+        fprintf(out, "%s", DESC(qpu_cond, cond));
+}
+
 static void
 print_alu_dst(uint64_t inst, bool is_mul)
 {
@@ -263,9 +288,9 @@ print_alu_dst(uint64_t inst, bool is_mul)
                 fprintf(stderr, "%s%d?", file, waddr);
 
         if (is_mul && (inst & QPU_PM)) {
-                fprintf(stderr, ".%s", DESC(qpu_pack_mul, pack));
+                vc4_qpu_disasm_pack_mul(stderr, pack);
         } else if (is_a && !(inst & QPU_PM)) {
-                fprintf(stderr, "%s", DESC(qpu_pack_a, pack));
+                vc4_qpu_disasm_pack_a(stderr, pack);
         }
 }
 
@@ -291,9 +316,9 @@ print_alu_src(uint64_t inst, uint32_t mux)
                 else if (si <= 39)
                         fprintf(stderr, "%.1f", (float)(1 << (si - 32)));
                 else if (si <= 47)
-                        fprintf(stderr, "%f", 1.0f / (256 / (si - 39)));
+                        fprintf(stderr, "%f", 1.0f / (1 << (48 - si)));
                 else
-                        fprintf(stderr, "???");
+                        fprintf(stderr, "<bad imm %d>", si);
         } else if (raddr <= 31)
                 fprintf(stderr, "r%s%d", file, raddr);
         else {
@@ -303,10 +328,9 @@ print_alu_src(uint64_t inst, uint32_t mux)
                         fprintf(stderr, "%s", DESC(special_read_b, raddr - 32));
         }
 
-        if (unpack != QPU_UNPACK_NOP &&
-            ((mux == QPU_MUX_A && !(inst & QPU_PM)) ||
+        if (((mux == QPU_MUX_A && !(inst & QPU_PM)) ||
              (mux == QPU_MUX_R4 && (inst & QPU_PM)))) {
-                fprintf(stderr, ".%s", DESC(qpu_unpack, unpack));
+                vc4_qpu_disasm_unpack(stderr, unpack);
         }
 }
 
@@ -319,11 +343,18 @@ print_add_op(uint64_t inst)
                        QPU_GET_FIELD(inst, QPU_ADD_A) ==
                        QPU_GET_FIELD(inst, QPU_ADD_B));
 
-        fprintf(stderr, "%s%s%s ",
-                is_mov ? "mov" : DESC(qpu_add_opcodes, op_add),
-                ((inst & QPU_SF) && op_add != QPU_A_NOP) ? ".sf" : "",
-                op_add != QPU_A_NOP ? DESC(qpu_condflags, cond) : "");
+        if (is_mov)
+                fprintf(stderr, "mov");
+        else
+                fprintf(stderr, "%s", DESC(qpu_add_opcodes, op_add));
+
+        if ((inst & QPU_SF) && op_add != QPU_A_NOP)
+                fprintf(stderr, ".sf");
+
+        if (op_add != QPU_A_NOP)
+                vc4_qpu_disasm_cond(stderr, cond);
 
+        fprintf(stderr, " ");
         print_alu_dst(inst, false);
         fprintf(stderr, ", ");
 
@@ -346,11 +377,18 @@ print_mul_op(uint64_t inst)
                        QPU_GET_FIELD(inst, QPU_MUL_A) ==
                        QPU_GET_FIELD(inst, QPU_MUL_B));
 
-        fprintf(stderr, "%s%s%s ",
-                is_mov ? "mov" : DESC(qpu_mul_opcodes, op_mul),
-                ((inst & QPU_SF) && op_add == QPU_A_NOP) ? ".sf" : "",
-                op_mul != QPU_M_NOP ? DESC(qpu_condflags, cond) : "");
+        if (is_mov)
+                fprintf(stderr, "mov");
+        else
+                fprintf(stderr, "%s", DESC(qpu_mul_opcodes, op_mul));
+
+        if ((inst & QPU_SF) && op_add == QPU_A_NOP)
+                fprintf(stderr, ".sf");
+
+        if (op_mul != QPU_M_NOP)
+                vc4_qpu_disasm_cond(stderr, cond);
 
+        fprintf(stderr, " ");
         print_alu_dst(inst, true);
         fprintf(stderr, ", ");
 
@@ -372,12 +410,17 @@ print_load_imm(uint64_t inst)
         uint32_t cond_mul = QPU_GET_FIELD(inst, QPU_COND_MUL);
 
         fprintf(stderr, "load_imm ");
+
         print_alu_dst(inst, false);
-        fprintf(stderr, "%s, ", (waddr_add != QPU_W_NOP ?
-                                 DESC(qpu_condflags, cond_add) : ""));
+        if (waddr_add != QPU_W_NOP)
+                vc4_qpu_disasm_cond(stderr, cond_add);
+        fprintf(stderr, ", ");
+
         print_alu_dst(inst, true);
-        fprintf(stderr, "%s, ", (waddr_mul != QPU_W_NOP ?
-                                 DESC(qpu_condflags, cond_mul) : ""));
+        if (waddr_mul != QPU_W_NOP)
+                vc4_qpu_disasm_cond(stderr, cond_mul);
+        fprintf(stderr, ", ");
+
         fprintf(stderr, "0x%08x (%f)", imm, uif(imm));
 }
 
@@ -390,7 +433,7 @@ vc4_qpu_disasm(const uint64_t *instructions, int num_instructions)
 
                 switch (sig) {
                 case QPU_SIG_BRANCH:
-                        fprintf(stderr, "branch\n");
+                        fprintf(stderr, "branch");
                         break;
                 case QPU_SIG_LOAD_IMM:
                         print_load_imm(inst);
@@ -401,10 +444,10 @@ vc4_qpu_disasm(const uint64_t *instructions, int num_instructions)
                         print_add_op(inst);
                         fprintf(stderr, " ; ");
                         print_mul_op(inst);
-
-                        if (num_instructions != 1)
-                                fprintf(stderr, "\n");
                         break;
                 }
+
+                if (num_instructions != 1)
+                        fprintf(stderr, "\n");
         }
 }