static void
vc4_dump_program(struct vc4_compile *c)
{
- fprintf(stderr, "%s:\n", qir_get_stage_name(c->stage));
+ fprintf(stderr, "%s prog %d/%d QPU:\n",
+ qir_get_stage_name(c->stage),
+ c->program_id, c->variant_id);
for (int i = 0; i < c->qpu_inst_count; i++) {
fprintf(stderr, "0x%016"PRIx64" ", c->qpu_insts[i]);
*last_inst(c) = qpu_set_cond_add(*last_inst(c), cond);
}
+/**
+ * Some special registers can be read from either file, which lets us resolve
+ * raddr conflicts without extra MOVs.
+ */
+static bool
+swap_file(struct qpu_reg *src)
+{
+ switch (src->addr) {
+ case QPU_R_UNIF:
+ case QPU_R_VARY:
+ if (src->mux == QPU_MUX_A)
+ src->mux = QPU_MUX_B;
+ else
+ src->mux = QPU_MUX_A;
+ return true;
+
+ default:
+ return false;
+ }
+}
+
/**
* This is used to resolve the fact that we might register-allocate two
* different operands of an instruction to the same physical register file
*/
static void
fixup_raddr_conflict(struct vc4_compile *c,
- struct qpu_reg src0, struct qpu_reg *src1)
+ struct qpu_reg *src0, struct qpu_reg *src1)
{
- if ((src0.mux == QPU_MUX_A || src0.mux == QPU_MUX_B) &&
- (src1->mux == QPU_MUX_A || src1->mux == QPU_MUX_B) &&
- src0.addr != src1->addr) {
- queue(c, qpu_a_MOV(qpu_r3(), *src1));
- *src1 = qpu_r3();
+ if ((src0->mux != QPU_MUX_A && src0->mux != QPU_MUX_B) ||
+ src0->mux != src1->mux ||
+ src0->addr == src1->addr) {
+ return;
}
+
+ if (swap_file(src0) || swap_file(src1))
+ return;
+
+ queue(c, qpu_a_MOV(qpu_r3(), *src1));
+ *src1 = qpu_r3();
}
static void
}
void
-vc4_generate_code(struct vc4_compile *c)
+vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c)
{
- struct qpu_reg *temp_registers = vc4_register_allocate(c);
+ struct qpu_reg *temp_registers = vc4_register_allocate(vc4, c);
bool discard = false;
+ uint32_t inputs_remaining = c->num_inputs;
+ uint32_t vpm_read_fifo_count = 0;
+ uint32_t vpm_read_offset = 0;
make_empty_list(&c->qpu_inst_list);
switch (c->stage) {
case QSTAGE_VERT:
case QSTAGE_COORD:
- queue(c, qpu_load_imm_ui(qpu_vrsetup(),
- (0x00001a00 +
- 0x00100000 * c->num_inputs)));
+ /* There's a 4-entry FIFO for VPMVCD reads, each of which can
+ * load up to 16 dwords (4 vec4s) per vertex.
+ */
+ while (inputs_remaining) {
+ uint32_t num_entries = MIN2(inputs_remaining, 16);
+ queue(c, qpu_load_imm_ui(qpu_vrsetup(),
+ vpm_read_offset |
+ 0x00001a00 |
+ ((num_entries & 0xf) << 20)));
+ inputs_remaining -= num_entries;
+ vpm_read_offset += num_entries;
+ vpm_read_fifo_count++;
+ }
+ assert(vpm_read_fifo_count <= 4);
+
queue(c, qpu_load_imm_ui(qpu_vwsetup(), 0x00001a00));
break;
case QSTAGE_FRAG:
qpu_rb(QPU_R_XY_PIXEL_COORD)));
break;
- case QOP_FRAG_Z:
- /* QOP_FRAG_Z doesn't emit instructions, just
- * allocates the register to the Z payload.
- */
+ case QOP_FRAG_REV_FLAG:
+ queue(c, qpu_a_ITOF(dst,
+ qpu_rb(QPU_R_MS_REV_FLAGS)));
break;
- case QOP_FRAG_RCP_W:
- queue(c, qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIP),
- qpu_ra(QPU_R_FRAG_PAYLOAD_ZW)));
-
- queue(c, qpu_a_MOV(dst, qpu_r4()));
+ case QOP_FRAG_Z:
+ case QOP_FRAG_W:
+ /* QOP_FRAG_Z/W don't emit instructions, just allocate
+ * the register to the Z/W payload.
+ */
break;
case QOP_TLB_DISCARD_SETUP:
*last_inst(c) |= QPU_SF;
break;
+ case QOP_TLB_STENCIL_SETUP:
+ queue(c, qpu_a_MOV(qpu_ra(QPU_W_TLB_STENCIL_SETUP), src[0]));
+ break;
+
case QOP_TLB_Z_WRITE:
queue(c, qpu_a_MOV(qpu_ra(QPU_W_TLB_Z), src[0]));
if (discard) {
assert(src[0].mux == QPU_MUX_R4);
queue(c, qpu_a_MOV(dst, src[0]));
*last_inst(c) |= QPU_PM;
- *last_inst(c) |= QPU_SET_FIELD(QPU_UNPACK_R4_8A +
+ *last_inst(c) |= QPU_SET_FIELD(QPU_UNPACK_8A +
(qinst->op -
QOP_R4_UNPACK_A),
QPU_UNPACK);
break;
+ case QOP_UNPACK_8A:
+ case QOP_UNPACK_8B:
+ case QOP_UNPACK_8C:
+ case QOP_UNPACK_8D: {
+ assert(src[0].mux == QPU_MUX_A);
+
+ /* And, since we're setting the pack bits, if the
+ * destination is in A it would get re-packed.
+ */
+ struct qpu_reg orig_dst = dst;
+ if (orig_dst.mux == QPU_MUX_A)
+ dst = qpu_rn(3);
+
+ queue(c, qpu_a_FMAX(dst, src[0], src[0]));
+ *last_inst(c) |= QPU_SET_FIELD(QPU_UNPACK_8A +
+ (qinst->op -
+ QOP_UNPACK_8A),
+ QPU_UNPACK);
+
+ if (orig_dst.mux == QPU_MUX_A) {
+ queue(c, qpu_a_MOV(orig_dst, dst));
+ }
+ }
+ break;
+
default:
assert(qinst->op < ARRAY_SIZE(translate));
assert(translate[qinst->op].op != 0); /* NOPs */
if (qir_get_op_nsrc(qinst->op) == 1)
src[1] = src[0];
- fixup_raddr_conflict(c, src[0], &src[1]);
+ fixup_raddr_conflict(c, &src[0], &src[1]);
if (translate[qinst->op].is_mul) {
queue(c, qpu_m_alu2(translate[qinst->op].op,
projects / mesa.git / blobdiff