vc4: Add support for 8-bit unorm/snorm vertex inputs.

[mesa.git] / src / gallium / drivers / vc4 / vc4_qpu_emit.c

diff --git a/src/gallium/drivers/vc4/vc4_qpu_emit.c b/src/gallium/drivers/vc4/vc4_qpu_emit.c
index 6c4c76d3217e1fa28508b0737e1ff180ce23008e..81b3b8bd78452329a1b251e799c72a2e5d6f448a 100644 (file)
--- a/src/gallium/drivers/vc4/vc4_qpu_emit.c
+++ b/src/gallium/drivers/vc4/vc4_qpu_emit.c
@@ -208,9 +208,9 @@ serialize_insts(struct vc4_compile *c)
 }
 
 void
-vc4_generate_code(struct vc4_compile *c)
+vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c)
 {
-        struct qpu_reg *temp_registers = vc4_register_allocate(c);
+        struct qpu_reg *temp_registers = vc4_register_allocate(vc4, c);
         bool discard = false;
 
         make_empty_list(&c->qpu_inst_list);
@@ -401,24 +401,22 @@ vc4_generate_code(struct vc4_compile *c)
                         break;
 
                 case QOP_FRAG_Z:
-                        /* QOP_FRAG_Z doesn't emit instructions, just
-                         * allocates the register to the Z payload.
+                case QOP_FRAG_W:
+                        /* QOP_FRAG_Z/W don't emit instructions, just allocate
+                         * the register to the Z/W payload.
                          */
                         break;
 
-                case QOP_FRAG_RCP_W:
-                        queue(c, qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIP),
-                                           qpu_ra(QPU_R_FRAG_PAYLOAD_ZW)));
-
-                        queue(c, qpu_a_MOV(dst, qpu_r4()));
-                        break;
-
                 case QOP_TLB_DISCARD_SETUP:
                         discard = true;
                         queue(c, qpu_a_MOV(src[0], src[0]));
                         *last_inst(c) |= QPU_SF;
                         break;
 
+                case QOP_TLB_STENCIL_SETUP:
+                        queue(c, qpu_a_MOV(qpu_ra(QPU_W_TLB_STENCIL_SETUP), src[0]));
+                        break;
+
                 case QOP_TLB_Z_WRITE:
                         queue(c, qpu_a_MOV(qpu_ra(QPU_W_TLB_Z), src[0]));
                         if (discard) {
@@ -485,13 +483,38 @@ vc4_generate_code(struct vc4_compile *c)
                         assert(src[0].mux == QPU_MUX_R4);
                         queue(c, qpu_a_MOV(dst, src[0]));
                         *last_inst(c) |= QPU_PM;
-                        *last_inst(c) |= QPU_SET_FIELD(QPU_UNPACK_R4_8A +
+                        *last_inst(c) |= QPU_SET_FIELD(QPU_UNPACK_8A +
                                                        (qinst->op -
                                                         QOP_R4_UNPACK_A),
                                                        QPU_UNPACK);
 
                         break;
 
+                case QOP_UNPACK_8A:
+                case QOP_UNPACK_8B:
+                case QOP_UNPACK_8C:
+                case QOP_UNPACK_8D: {
+                        assert(src[0].mux == QPU_MUX_A);
+
+                        /* And, since we're setting the pack bits, if the
+                         * destination is in A it would get re-packed.
+                         */
+                        struct qpu_reg orig_dst = dst;
+                        if (orig_dst.mux == QPU_MUX_A)
+                                dst = qpu_rn(3);
+
+                        queue(c, qpu_a_FMAX(dst, src[0], src[0]));
+                        *last_inst(c) |= QPU_SET_FIELD(QPU_UNPACK_8A +
+                                                       (qinst->op -
+                                                        QOP_UNPACK_8A),
+                                                       QPU_UNPACK);
+
+                        if (orig_dst.mux == QPU_MUX_A) {
+                                queue(c, qpu_a_MOV(orig_dst, dst));
+                        }
+                }
+                        break;
+
                 default:
                         assert(qinst->op < ARRAY_SIZE(translate));
                         assert(translate[qinst->op].op != 0); /* NOPs */
@@ -528,6 +551,14 @@ vc4_generate_code(struct vc4_compile *c)
                 serialize_one_inst(c, qpu_NOP());
         }
 
+        /* thread end can't have uniform read */
+        if (QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
+                          QPU_RADDR_A) == QPU_R_UNIF ||
+            QPU_GET_FIELD(c->qpu_insts[c->qpu_inst_count - 1],
+                          QPU_RADDR_B) == QPU_R_UNIF) {
+                serialize_one_inst(c, qpu_NOP());
+        }
+
         c->qpu_insts[c->qpu_inst_count - 1] =
                 qpu_set_sig(c->qpu_insts[c->qpu_inst_count - 1],
                             QPU_SIG_PROG_END);