uint32_t child_array_size;
uint32_t parent_count;
+ /* Longest cycles + instruction_latency() of any parent of this node. */
+ uint32_t unblocked_time;
+
/**
* Minimum number of cycles from scheduling this instruction until the
* end of the program, based on the slowest dependency chain through
struct schedule_node *last_tlb;
struct schedule_node *last_vpm;
enum direction dir;
+ /* Estimated cycle when the current instruction would start. */
+ uint32_t time;
};
static void
}
} else if (is_tmu_write(waddr)) {
add_write_dep(state, &state->last_tmu_write, n);
- } else if (qpu_waddr_is_tlb(waddr)) {
+ } else if (qpu_waddr_is_tlb(waddr) ||
+ waddr == QPU_W_MS_FLAGS) {
add_write_dep(state, &state->last_tlb, n);
} else {
switch (waddr) {
add_write_dep(state, &state->last_tlb, n);
break;
+ case QPU_W_MS_FLAGS:
+ add_write_dep(state, &state->last_tlb, n);
+ break;
+
case QPU_W_NOP:
break;
}
process_cond_deps(state, n, QPU_GET_FIELD(inst, QPU_COND_ADD));
- process_cond_deps(state, n, QPU_GET_FIELD(inst, QPU_COND_ADD));
+ process_cond_deps(state, n, QPU_GET_FIELD(inst, QPU_COND_MUL));
if (inst & QPU_SF)
add_write_dep(state, &state->last_sf, n);
}
static void
dump_state(struct list_head *schedule_list)
{
- uint32_t i = 0;
-
list_for_each_entry(struct schedule_node, n, schedule_list, link) {
- fprintf(stderr, "%3d: ", i++);
+ fprintf(stderr, " t=%4d: ", n->unblocked_time);
vc4_qpu_disasm(&n->inst->inst, 1);
fprintf(stderr, "\n");
if (!child)
continue;
- fprintf(stderr, " - ");
+ fprintf(stderr, " - ");
vc4_qpu_disasm(&child->inst->inst, 1);
fprintf(stderr, " (%d parents, %c)\n",
child->parent_count,
}
}
+static uint32_t waddr_latency(uint32_t waddr, uint64_t after)
+{
+ if (waddr < 32)
+ return 2;
+
+ /* Apply some huge latency between texture fetch requests and getting
+ * their results back.
+ */
+ if (waddr == QPU_W_TMU0_S) {
+ if (QPU_GET_FIELD(after, QPU_SIG) == QPU_SIG_LOAD_TMU0)
+ return 100;
+ }
+ if (waddr == QPU_W_TMU1_S) {
+ if (QPU_GET_FIELD(after, QPU_SIG) == QPU_SIG_LOAD_TMU1)
+ return 100;
+ }
+
+ switch(waddr) {
+ case QPU_W_SFU_RECIP:
+ case QPU_W_SFU_RECIPSQRT:
+ case QPU_W_SFU_EXP:
+ case QPU_W_SFU_LOG:
+ return 3;
+ default:
+ return 1;
+ }
+}
+
+static uint32_t
+instruction_latency(struct schedule_node *before, struct schedule_node *after)
+{
+ uint64_t before_inst = before->inst->inst;
+ uint64_t after_inst = after->inst->inst;
+
+ return MAX2(waddr_latency(QPU_GET_FIELD(before_inst, QPU_WADDR_ADD),
+ after_inst),
+ waddr_latency(QPU_GET_FIELD(before_inst, QPU_WADDR_MUL),
+ after_inst));
+}
+
/** Recursive computation of the delay member of a node. */
static void
compute_delay(struct schedule_node *n)
if (!n->children[i].node->delay)
compute_delay(n->children[i].node);
n->delay = MAX2(n->delay,
- n->children[i].node->delay + n->latency);
+ n->children[i].node->delay +
+ instruction_latency(n, n->children[i].node));
}
}
}
static void
mark_instruction_scheduled(struct list_head *schedule_list,
+ uint32_t time,
struct schedule_node *node,
bool war_only)
{
if (war_only && !node->children[i].write_after_read)
continue;
+ /* If the requirement is only that the node not appear before
+ * the last read of its destination, then it can be scheduled
+ * immediately after (or paired with!) the thing reading the
+ * destination.
+ */
+ uint32_t latency = 0;
+ if (!war_only) {
+ latency = instruction_latency(node,
+ node->children[i].node);
+ }
+
+ child->unblocked_time = MAX2(child->unblocked_time,
+ time + latency);
child->parent_count--;
if (child->parent_count == 0)
list_add(&child->link, schedule_list);
}
}
-static void
-schedule_instructions(struct vc4_compile *c, struct list_head *schedule_list)
+static uint32_t
+schedule_instructions(struct vc4_compile *c, struct list_head *schedule_list,
+ enum quniform_contents *orig_uniform_contents,
+ uint32_t *orig_uniform_data,
+ uint32_t *next_uniform)
{
struct choose_scoreboard scoreboard;
-
- /* We reorder the uniforms as we schedule instructions, so save the
- * old data off and replace it.
- */
- uint32_t *uniform_data = c->uniform_data;
- enum quniform_contents *uniform_contents = c->uniform_contents;
- c->uniform_contents = ralloc_array(c, enum quniform_contents,
- c->num_uniforms);
- c->uniform_data = ralloc_array(c, uint32_t, c->num_uniforms);
- c->uniform_array_size = c->num_uniforms;
- uint32_t next_uniform = 0;
+ uint32_t time = 0;
memset(&scoreboard, 0, sizeof(scoreboard));
scoreboard.last_waddr_a = ~0;
uint64_t inst = chosen ? chosen->inst->inst : qpu_NOP();
if (debug) {
- fprintf(stderr, "current list:\n");
+ fprintf(stderr, "t=%4d: current list:\n",
+ time);
dump_state(schedule_list);
- fprintf(stderr, "chose: ");
+ fprintf(stderr, "t=%4d: chose: ", time);
vc4_qpu_disasm(&inst, 1);
fprintf(stderr, "\n");
}
* find an instruction to pair with it.
*/
if (chosen) {
+ time = MAX2(chosen->unblocked_time, time);
list_del(&chosen->link);
- mark_instruction_scheduled(schedule_list, chosen, true);
+ mark_instruction_scheduled(schedule_list, time,
+ chosen, true);
if (chosen->uniform != -1) {
- c->uniform_data[next_uniform] =
- uniform_data[chosen->uniform];
- c->uniform_contents[next_uniform] =
- uniform_contents[chosen->uniform];
- next_uniform++;
+ c->uniform_data[*next_uniform] =
+ orig_uniform_data[chosen->uniform];
+ c->uniform_contents[*next_uniform] =
+ orig_uniform_contents[chosen->uniform];
+ (*next_uniform)++;
}
merge = choose_instruction_to_schedule(&scoreboard,
schedule_list,
chosen);
if (merge) {
+ time = MAX2(merge->unblocked_time, time);
list_del(&merge->link);
inst = qpu_merge_inst(inst, merge->inst->inst);
assert(inst != 0);
if (merge->uniform != -1) {
- c->uniform_data[next_uniform] =
- uniform_data[merge->uniform];
- c->uniform_contents[next_uniform] =
- uniform_contents[merge->uniform];
- next_uniform++;
+ c->uniform_data[*next_uniform] =
+ orig_uniform_data[merge->uniform];
+ c->uniform_contents[*next_uniform] =
+ orig_uniform_contents[merge->uniform];
+ (*next_uniform)++;
}
if (debug) {
- fprintf(stderr, "merging: ");
+ fprintf(stderr, "t=%4d: merging: ",
+ time);
vc4_qpu_disasm(&merge->inst->inst, 1);
fprintf(stderr, "\n");
- fprintf(stderr, "resulting in: ");
+ fprintf(stderr, " resulting in: ");
vc4_qpu_disasm(&inst, 1);
fprintf(stderr, "\n");
}
* be scheduled. Update the children's unblocked time for this
* DAG edge as we do so.
*/
- mark_instruction_scheduled(schedule_list, chosen, false);
- mark_instruction_scheduled(schedule_list, merge, false);
+ mark_instruction_scheduled(schedule_list, time, chosen, false);
+ mark_instruction_scheduled(schedule_list, time, merge, false);
scoreboard.tick++;
+ time++;
}
- assert(next_uniform == c->num_uniforms);
-}
-
-static uint32_t waddr_latency(uint32_t waddr)
-{
- if (waddr < 32)
- return 2;
-
- /* Some huge number, really. */
- if (waddr >= QPU_W_TMU0_S && waddr <= QPU_W_TMU1_B)
- return 10;
-
- switch(waddr) {
- case QPU_W_SFU_RECIP:
- case QPU_W_SFU_RECIPSQRT:
- case QPU_W_SFU_EXP:
- case QPU_W_SFU_LOG:
- return 3;
- default:
- return 1;
- }
+ return time;
}
static uint32_t
-instruction_latency(uint64_t inst)
-{
- return MAX2(waddr_latency(QPU_GET_FIELD(inst, QPU_WADDR_ADD)),
- waddr_latency(QPU_GET_FIELD(inst, QPU_WADDR_MUL)));
-}
-
-void
-qpu_schedule_instructions(struct vc4_compile *c)
+qpu_schedule_instructions_block(struct vc4_compile *c, struct qblock *block,
+ enum quniform_contents *orig_uniform_contents,
+ uint32_t *orig_uniform_data,
+ uint32_t *next_uniform)
{
void *mem_ctx = ralloc_context(NULL);
struct list_head schedule_list;
list_inithead(&schedule_list);
- if (debug) {
- fprintf(stderr, "Pre-schedule instructions\n");
- list_for_each_entry(struct queued_qpu_inst, q,
- &c->qpu_inst_list, link) {
- vc4_qpu_disasm(&q->inst, 1);
- fprintf(stderr, "\n");
- }
- fprintf(stderr, "\n");
- }
-
/* Wrap each instruction in a scheduler structure. */
- uint32_t next_uniform = 0;
- while (!list_empty(&c->qpu_inst_list)) {
+ uint32_t next_sched_uniform = *next_uniform;
+ while (!list_empty(&block->qpu_inst_list)) {
struct queued_qpu_inst *inst =
- (struct queued_qpu_inst *)c->qpu_inst_list.next;
+ (struct queued_qpu_inst *)block->qpu_inst_list.next;
struct schedule_node *n = rzalloc(mem_ctx, struct schedule_node);
n->inst = inst;
- n->latency = instruction_latency(inst->inst);
if (reads_uniform(inst->inst)) {
- n->uniform = next_uniform++;
+ n->uniform = next_sched_uniform++;
} else {
n->uniform = -1;
}
list_del(&inst->link);
list_addtail(&n->link, &schedule_list);
}
- assert(next_uniform == c->num_uniforms);
calculate_forward_deps(c, &schedule_list);
calculate_reverse_deps(c, &schedule_list);
compute_delay(n);
}
- schedule_instructions(c, &schedule_list);
+ uint32_t cycles = schedule_instructions(c, &schedule_list,
+ orig_uniform_contents,
+ orig_uniform_data,
+ next_uniform);
+
+ ralloc_free(mem_ctx);
+
+ return cycles;
+}
+
+uint32_t
+qpu_schedule_instructions(struct vc4_compile *c)
+{
+ /* We reorder the uniforms as we schedule instructions, so save the
+ * old data off and replace it.
+ */
+ uint32_t *uniform_data = c->uniform_data;
+ enum quniform_contents *uniform_contents = c->uniform_contents;
+ c->uniform_contents = ralloc_array(c, enum quniform_contents,
+ c->num_uniforms);
+ c->uniform_data = ralloc_array(c, uint32_t, c->num_uniforms);
+ c->uniform_array_size = c->num_uniforms;
+ uint32_t next_uniform = 0;
+
+ if (debug) {
+ fprintf(stderr, "Pre-schedule instructions\n");
+ qir_for_each_block(block, c) {
+ fprintf(stderr, "BLOCK %d\n", block->index);
+ list_for_each_entry(struct queued_qpu_inst, q,
+ &block->qpu_inst_list, link) {
+ vc4_qpu_disasm(&q->inst, 1);
+ fprintf(stderr, "\n");
+ }
+ }
+ fprintf(stderr, "\n");
+ }
+
+ uint32_t cycles = 0;
+ qir_for_each_block(block, c) {
+ cycles += qpu_schedule_instructions_block(c, block,
+ uniform_contents,
+ uniform_data,
+ &next_uniform);
+ }
+
+ assert(next_uniform == c->num_uniforms);
if (debug) {
fprintf(stderr, "Post-schedule instructions\n");
fprintf(stderr, "\n");
}
- ralloc_free(mem_ctx);
+ return cycles;
}
projects / mesa.git / blobdiff