vc4->regs = ra_alloc_reg_set(vc4, ARRAY_SIZE(vc4_regs), true);
vc4->reg_class_any = ra_alloc_reg_class(vc4->regs);
+ vc4->reg_class_a_or_b_or_acc = ra_alloc_reg_class(vc4->regs);
vc4->reg_class_r4_or_a = ra_alloc_reg_class(vc4->regs);
vc4->reg_class_a = ra_alloc_reg_class(vc4->regs);
for (uint32_t i = 0; i < ARRAY_SIZE(vc4_regs); i++) {
*/
if (vc4_regs[i].mux == QPU_MUX_R4) {
ra_class_add_reg(vc4->regs, vc4->reg_class_r4_or_a, i);
+ ra_class_add_reg(vc4->regs, vc4->reg_class_any, i);
continue;
}
ra_class_add_reg(vc4->regs, vc4->reg_class_any, i);
+ ra_class_add_reg(vc4->regs, vc4->reg_class_a_or_b_or_acc, i);
}
for (uint32_t i = AB_INDEX; i < AB_INDEX + 64; i += 2) {
{
struct node_to_temp_map map[c->num_temps];
uint32_t temp_to_node[c->num_temps];
- uint32_t def[c->num_temps];
- uint32_t use[c->num_temps];
uint8_t class_bits[c->num_temps];
struct qpu_reg *temp_registers = calloc(c->num_temps,
sizeof(*temp_registers));
- for (int i = 0; i < ARRAY_SIZE(def); i++)
- def[i] = ~0;
- memset(use, 0, sizeof(use));
/* If things aren't ever written (undefined values), just read from
* r0.
struct ra_graph *g = ra_alloc_interference_graph(vc4->regs,
c->num_temps);
- /* Compute the live ranges so we can figure out interference.
- */
- uint32_t ip = 0;
- list_for_each_entry(struct qinst, inst, &c->instructions, link) {
- if (inst->dst.file == QFILE_TEMP) {
- def[inst->dst.index] = MIN2(ip, def[inst->dst.index]);
- use[inst->dst.index] = ip;
- }
-
- for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
- if (inst->src[i].file == QFILE_TEMP)
- use[inst->src[i].index] = ip;
- }
-
- switch (inst->op) {
- case QOP_FRAG_Z:
- case QOP_FRAG_W:
- /* The payload registers have values implicitly loaded
- * at the start of the program.
- */
- def[inst->dst.index] = 0;
- break;
- default:
- break;
- }
-
- ip++;
- }
+ /* Compute the live ranges so we can figure out interference. */
+ qir_calculate_live_intervals(c);
for (uint32_t i = 0; i < c->num_temps; i++) {
map[i].temp = i;
- map[i].priority = use[i] - def[i];
+ map[i].priority = c->temp_end[i] - c->temp_start[i];
}
qsort(map, c->num_temps, sizeof(map[0]), node_to_temp_priority);
for (uint32_t i = 0; i < c->num_temps; i++) {
CLASS_BIT_A | CLASS_BIT_B_OR_ACC | CLASS_BIT_R4,
sizeof(class_bits));
- ip = 0;
- list_for_each_entry(struct qinst, inst, &c->instructions, link) {
+ int ip = 0;
+ qir_for_each_inst_inorder(inst, c) {
if (qir_writes_r4(inst)) {
/* This instruction writes r4 (and optionally moves
* its result to a temp), so nothing else can be
* stored in r4 across it.
*/
for (int i = 0; i < c->num_temps; i++) {
- if (def[i] < ip && use[i] > ip)
+ if (c->temp_start[i] < ip && c->temp_end[i] > ip)
class_bits[i] &= ~CLASS_BIT_R4;
}
} else {
AB_INDEX + QPU_R_FRAG_PAYLOAD_ZW * 2);
break;
- case QOP_PACK_16A_I:
- case QOP_PACK_16B_I:
- /* The pack flags require an A-file dst register. */
- class_bits[inst->dst.index] &= CLASS_BIT_A;
- break;
-
default:
break;
}
- if (qir_src_needs_a_file(inst)) {
- class_bits[inst->src[0].index] &= CLASS_BIT_A;
+ if (inst->dst.pack && !qir_is_mul(inst)) {
+ /* The non-MUL pack flags require an A-file dst
+ * register.
+ */
+ class_bits[inst->dst.index] &= CLASS_BIT_A;
}
+
+ /* Apply restrictions for src unpacks. The integer unpacks
+ * can only be done from regfile A, while float unpacks can be
+ * either A or R4.
+ */
+ for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
+ if (inst->src[i].file == QFILE_TEMP &&
+ inst->src[i].pack) {
+ if (qir_is_float_input(inst)) {
+ class_bits[inst->src[i].index] &=
+ CLASS_BIT_A | CLASS_BIT_R4;
+ } else {
+ class_bits[inst->src[i].index] &=
+ CLASS_BIT_A;
+ }
+ }
+ }
+
ip++;
}
switch (class_bits[i]) {
case CLASS_BIT_A | CLASS_BIT_B_OR_ACC | CLASS_BIT_R4:
- case CLASS_BIT_A | CLASS_BIT_B_OR_ACC:
ra_set_node_class(g, node, vc4->reg_class_any);
break;
+ case CLASS_BIT_A | CLASS_BIT_B_OR_ACC:
+ ra_set_node_class(g, node, vc4->reg_class_a_or_b_or_acc);
+ break;
case CLASS_BIT_A | CLASS_BIT_R4:
ra_set_node_class(g, node, vc4->reg_class_r4_or_a);
break;
for (uint32_t i = 0; i < c->num_temps; i++) {
for (uint32_t j = i + 1; j < c->num_temps; j++) {
- if (!(def[i] >= use[j] || def[j] >= use[i])) {
+ if (!(c->temp_start[i] >= c->temp_end[j] ||
+ c->temp_start[j] >= c->temp_end[i])) {
ra_add_node_interference(g,
temp_to_node[i],
temp_to_node[j]);
/* If the value's never used, just write to the NOP register
* for clarity in debug output.
*/
- if (def[i] == use[i])
+ if (c->temp_start[i] == c->temp_end[i])
temp_registers[i] = qpu_ra(QPU_W_NOP);
}
projects / mesa.git / blobdiff