broadcom/vc5: Fix alignment of miplevel 1 with UIF.

[mesa.git] / src / gallium / drivers / vc5 / vc5_resource.h

diff --git a/src/gallium/drivers/vc5/vc5_resource.h b/src/gallium/drivers/vc5/vc5_resource.h
index 688f03d53f50abbb71301c82e30006d5f2007b4c..1bba480115b01efb96eb8b35f4e7d03271a9522c 100644 (file)
--- a/src/gallium/drivers/vc5/vc5_resource.h
+++ b/src/gallium/drivers/vc5/vc5_resource.h
@@ -73,16 +73,16 @@ struct vc5_transfer {
 struct vc5_resource_slice {
         uint32_t offset;
         uint32_t stride;
+        uint32_t padded_height;
         uint32_t size;
+        uint8_t ub_pad;
         enum vc5_tiling_mode tiling;
 };
 
 struct vc5_surface {
         struct pipe_surface base;
         uint32_t offset;
-        uint32_t separate_stencil_offset;
         enum vc5_tiling_mode tiling;
-        enum vc5_tiling_mode separate_stencil_tiling;
         /**
          * Output image format for TILE_RENDERING_MODE_CONFIGURATION
          */
@@ -101,7 +101,11 @@ struct vc5_surface {
         uint8_t internal_bpp;
 
         uint32_t padded_height_of_output_image_in_uif_blocks;
-        uint32_t separate_stencil_padded_height_of_output_image_in_uif_blocks;
+
+        /* If the resource being referenced is separate stencil, then this is
+         * the surface to use when reading/writing stencil.
+         */
+        struct pipe_surface *separate_stencil;
 };
 
 struct vc5_resource {