radeonsi: move PKT3_WRITE_DATA generation into a helper function

[mesa.git] / src / gallium / drivers / virgl / virgl_context.h

diff --git a/src/gallium/drivers/virgl/virgl_context.h b/src/gallium/drivers/virgl/virgl_context.h
index 3492dcfa494fe25ddbd3d8812b8a2c6ba0153bac..79a1a73e615fe68488cc253b8bb2136e8f3338ba 100644 (file)
--- a/src/gallium/drivers/virgl/virgl_context.h
+++ b/src/gallium/drivers/virgl/virgl_context.h
@@ -32,6 +32,7 @@ struct pipe_screen;
 struct tgsi_token;
 struct u_upload_mgr;
 struct virgl_cmd_buf;
+struct virgl_vertex_elements_state;
 
 struct virgl_sampler_view {
    struct pipe_sampler_view base;
@@ -48,15 +49,21 @@ struct virgl_textures_info {
    uint32_t enabled_mask;
 };
 
+struct virgl_rasterizer_state {
+   struct pipe_rasterizer_state rs;
+   uint32_t handle;
+};
+
 struct virgl_context {
    struct pipe_context base;
    struct virgl_cmd_buf *cbuf;
 
    struct virgl_textures_info samplers[PIPE_SHADER_TYPES];
+   struct virgl_vertex_elements_state *vertex_elements;
 
    struct pipe_framebuffer_state framebuffer;
 
-   struct slab_child_pool texture_transfer_pool;
+   struct slab_child_pool transfer_pool;
 
    struct u_upload_mgr *uploader;
 
@@ -64,13 +71,18 @@ struct virgl_context {
    unsigned num_vertex_buffers;
    boolean vertex_array_dirty;
 
+   struct virgl_rasterizer_state rs_state;
    struct virgl_so_target so_targets[PIPE_MAX_SO_BUFFERS];
    unsigned num_so_targets;
 
    struct pipe_resource *ubos[PIPE_SHADER_TYPES][PIPE_MAX_CONSTANT_BUFFERS];
+
+   struct pipe_resource *ssbos[PIPE_SHADER_TYPES][PIPE_MAX_SHADER_BUFFERS];
+   struct pipe_resource *images[PIPE_SHADER_TYPES][PIPE_MAX_SHADER_BUFFERS];
    int num_transfers;
    int num_draws;
-   struct list_head to_flush_bufs;
+
+   struct pipe_resource *atomic_buffers[PIPE_MAX_HW_ATOMIC_BUFFERS];
 
    struct primconvert_context *primconvert;
    uint32_t hw_sub_ctx_id;