virgl: define MAX_VERTEX_STREAMS based on availability of TF3
[mesa.git] / src / gallium / drivers / virgl / virgl_screen.c
index 0ac976acbd380905dac709c5347796f26cc3d0be..5dd7f559948c42350719a12f9089344c71d1f267 100644 (file)
@@ -23,7 +23,9 @@
 #include "util/u_memory.h"
 #include "util/u_format.h"
 #include "util/u_format_s3tc.h"
+#include "util/u_screen.h"
 #include "util/u_video.h"
+#include "util/u_math.h"
 #include "util/os_time.h"
 #include "pipe/p_defines.h"
 #include "pipe/p_screen.h"
 #include "virgl_public.h"
 #include "virgl_context.h"
 
+int virgl_debug = 0;
+static const struct debug_named_value debug_options[] = {
+   { "verbose", VIRGL_DEBUG_VERBOSE, NULL },
+   { "tgsi", VIRGL_DEBUG_TGSI, NULL },
+   DEBUG_NAMED_VALUE_END
+};
+DEBUG_GET_ONCE_FLAGS_OPTION(virgl_debug, "VIRGL_DEBUG", debug_options, 0)
+
 static const char *
 virgl_get_vendor(struct pipe_screen *screen)
 {
@@ -68,14 +78,21 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_OCCLUSION_QUERY:
       return vscreen->caps.caps.v1.bset.occlusion_query;
    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
+   case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
       return vscreen->caps.caps.v1.bset.mirror_clamp;
    case PIPE_CAP_TEXTURE_SWIZZLE:
       return 1;
    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
+      if (vscreen->caps.caps.v2.max_texture_2d_size)
+         return 1 + util_logbase2(vscreen->caps.caps.v2.max_texture_2d_size);
       return 15; /* 16K x 16K */
    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
+      if (vscreen->caps.caps.v2.max_texture_3d_size)
+         return 1 + util_logbase2(vscreen->caps.caps.v2.max_texture_3d_size);
       return 9; /* 256 x 256 x 256 */
    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
+      if (vscreen->caps.caps.v2.max_texture_cube_size)
+         return 1 + util_logbase2(vscreen->caps.caps.v2.max_texture_cube_size);
       return 13; /* 4K x 4K */
    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
       return 1;
@@ -127,12 +144,14 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
       return vscreen->caps.caps.v1.bset.color_clamping;
    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
-      return 1;
+      return (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FBO_MIXED_COLOR_FORMATS) ||
+            (vscreen->caps.caps.v2.host_feature_check_version < 1);
    case PIPE_CAP_GLSL_FEATURE_LEVEL:
       return vscreen->caps.caps.v1.glsl_level;
    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
       return MIN2(vscreen->caps.caps.v1.glsl_level, 140);
    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
+   case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
       return 0;
    case PIPE_CAP_COMPUTE:
       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER;
@@ -154,7 +173,7 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_QUERY_TIMESTAMP:
       return 1;
    case PIPE_CAP_QUERY_TIME_ELAPSED:
-      return 0;
+      return 1;
    case PIPE_CAP_TGSI_TEXCOORD:
       return 0;
    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
@@ -198,7 +217,8 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_CULL_DISTANCE:
       return vscreen->caps.caps.v1.bset.has_cull;
    case PIPE_CAP_MAX_VERTEX_STREAMS:
-      return vscreen->caps.caps.v1.glsl_level >= 400 ? 4 : 1;
+      return ((vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TRANSFORM_FEEDBACK3) ||
+              (vscreen->caps.caps.v2.host_feature_check_version < 2)) ? 4 : 1;
    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
       return vscreen->caps.caps.v1.bset.conditional_render_inverted;
    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
@@ -210,7 +230,8 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
       return vscreen->caps.caps.v2.shader_buffer_offset_alignment;
    case PIPE_CAP_DOUBLES:
-      return vscreen->caps.caps.v1.bset.has_fp64;
+      return vscreen->caps.caps.v1.bset.has_fp64 ||
+            (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FAKE_FP64);
    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
       return vscreen->caps.caps.v2.max_shader_patch_varyings;
    case PIPE_CAP_SAMPLER_VIEW_TARGET:
@@ -229,9 +250,29 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TGSI_FBFETCH;
    case PIPE_CAP_TGSI_CLOCK:
       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SHADER_CLOCK;
+   case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
+      return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TGSI_COMPONENTS;
+   case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
+      return vscreen->caps.caps.v2.max_combined_shader_buffers;
+   case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
+      return vscreen->caps.caps.v2.max_combined_atomic_counters;
+   case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
+      return vscreen->caps.caps.v2.max_combined_atomic_counter_buffers;
+   case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
+   case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
+      return 1; /* TODO: need to introduce a hw-cap for this */
+   case PIPE_CAP_QUERY_BUFFER_OBJECT:
+      return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_QBO;
+   case PIPE_CAP_MAX_VARYINGS:
+      if (vscreen->caps.caps.v1.glsl_level < 150)
+         return vscreen->caps.caps.v2.max_vertex_attribs;
+      return 32;
+   case PIPE_CAP_FAKE_SW_MSAA:
+      /* If the host supports only one sample (e.g., if it is using softpipe),
+       * fake multisampling to able to advertise higher GL versions. */
+      return (vscreen->caps.caps.v1.max_samples == 1) ? 1 : 0;
    case PIPE_CAP_TEXTURE_GATHER_SM5:
    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
-   case PIPE_CAP_FAKE_SW_MSAA:
    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
    case PIPE_CAP_MULTI_DRAW_INDIRECT:
@@ -241,8 +282,6 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
-   case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
-   case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
    case PIPE_CAP_DEPTH_BOUNDS_TEST:
    case PIPE_CAP_SHAREABLE_SHADERS:
    case PIPE_CAP_CLEAR_TEXTURE:
@@ -253,7 +292,6 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_INVALIDATE_BUFFER:
    case PIPE_CAP_GENERATE_MIPMAP:
    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
-   case PIPE_CAP_QUERY_BUFFER_OBJECT:
    case PIPE_CAP_STRING_MARKER:
    case PIPE_CAP_QUERY_MEMORY_INFO:
    case PIPE_CAP_PCI_GROUP:
@@ -265,7 +303,6 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
-   case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
@@ -299,7 +336,12 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
+   case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
       return 0;
+   case PIPE_CAP_MAX_GS_INVOCATIONS:
+      return 32;
+   case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
+      return 1 << 27;
    case PIPE_CAP_VENDOR_ID:
       return 0x1af4;
    case PIPE_CAP_DEVICE_ID:
@@ -310,11 +352,12 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_VIDEO_MEMORY:
       return 0;
    case PIPE_CAP_NATIVE_FENCE_FD:
-      return 0;
+      return vscreen->vws->supports_fences;
+   case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
+      return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SRGB_WRITE_CONTROL;
+   default:
+      return u_pipe_screen_get_param_defaults(screen, param);
    }
-   /* should only get here on unhandled cases */
-   debug_printf("Unexpected PIPE_CAP %d query\n", param);
-   return 0;
 }
 
 static int
@@ -389,12 +432,14 @@ virgl_get_shader_param(struct pipe_screen *screen,
             return vscreen->caps.caps.v2.max_shader_image_other_stages;
       case PIPE_SHADER_CAP_SUPPORTED_IRS:
          return (1 << PIPE_SHADER_IR_TGSI);
+      case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
+         return vscreen->caps.caps.v2.max_atomic_counters[shader];
+      case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
+         return vscreen->caps.caps.v2.max_atomic_counter_buffers[shader];
       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
       case PIPE_SHADER_CAP_INT64_ATOMICS:
       case PIPE_SHADER_CAP_FP16:
-      case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
-      case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
          return 0;
       case PIPE_SHADER_CAP_SCALAR_ISA:
          return 1;
@@ -571,6 +616,9 @@ virgl_is_format_supported( struct pipe_screen *screen,
       return virgl_is_vertex_format_supported(screen, format);
    }
 
+   if (util_format_is_compressed(format) && target == PIPE_BUFFER)
+      return FALSE;
+
    /* Allow 3-comp 32 bit textures only for TBOs (needed for ARB_tbo_rgb32) */
    if ((format == PIPE_FORMAT_R32G32B32_FLOAT ||
        format == PIPE_FORMAT_R32G32B32_SINT ||
@@ -578,6 +626,12 @@ virgl_is_format_supported( struct pipe_screen *screen,
        target != PIPE_BUFFER)
       return FALSE;
 
+   if ((format_desc->layout == UTIL_FORMAT_LAYOUT_RGTC ||
+        format_desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
+        format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) &&
+       target == PIPE_TEXTURE_3D)
+      return FALSE;
+
    if (bind & PIPE_BIND_RENDER_TARGET) {
       /* For ARB_framebuffer_no_attachments. */
       if (format == PIPE_FORMAT_NONE)
@@ -690,6 +744,15 @@ static boolean virgl_fence_finish(struct pipe_screen *screen,
    return vws->fence_wait(vws, fence, timeout);
 }
 
+static int virgl_fence_get_fd(struct pipe_screen *screen,
+            struct pipe_fence_handle *fence)
+{
+   struct virgl_screen *vscreen = virgl_screen(screen);
+   struct virgl_winsys *vws = vscreen->vws;
+
+   return vws->fence_get_fd(vws, fence);
+}
+
 static uint64_t
 virgl_get_timestamp(struct pipe_screen *_screen)
 {
@@ -702,7 +765,7 @@ virgl_destroy_screen(struct pipe_screen *screen)
    struct virgl_screen *vscreen = virgl_screen(screen);
    struct virgl_winsys *vws = vscreen->vws;
 
-   slab_destroy_parent(&vscreen->texture_transfer_pool);
+   slab_destroy_parent(&vscreen->transfer_pool);
 
    if (vws)
       vws->destroy(vws);
@@ -717,6 +780,8 @@ virgl_create_screen(struct virgl_winsys *vws)
    if (!screen)
       return NULL;
 
+   virgl_debug = debug_get_option_virgl_debug();
+
    screen->vws = vws;
    screen->base.get_name = virgl_get_name;
    screen->base.get_vendor = virgl_get_vendor;
@@ -732,6 +797,7 @@ virgl_create_screen(struct virgl_winsys *vws)
    screen->base.fence_reference = virgl_fence_reference;
    //screen->base.fence_signalled = virgl_fence_signalled;
    screen->base.fence_finish = virgl_fence_finish;
+   screen->base.fence_get_fd = virgl_fence_get_fd;
 
    virgl_init_screen_resource_functions(&screen->base);
 
@@ -739,7 +805,7 @@ virgl_create_screen(struct virgl_winsys *vws)
 
    screen->refcnt = 1;
 
-   slab_create_parent(&screen->texture_transfer_pool, sizeof(struct virgl_transfer), 16);
+   slab_create_parent(&screen->transfer_pool, sizeof(struct virgl_transfer), 16);
 
    return &screen->base;
 }