radeonsi/gfx10: update a tunable max_es_verts_base for NGG
[mesa.git] / src / gallium / drivers / virgl / virgl_screen.c
index be684dbf3c14b9ea0fc11bdf5f02cebdb761304e..db3a520508ef1d388e766d621c0a10ea895e6008 100644 (file)
 
 int virgl_debug = 0;
 static const struct debug_named_value debug_options[] = {
-   { "verbose", VIRGL_DEBUG_VERBOSE, NULL },
-   { "tgsi", VIRGL_DEBUG_TGSI, NULL },
+   { "verbose",   VIRGL_DEBUG_VERBOSE,             NULL },
+   { "tgsi",      VIRGL_DEBUG_TGSI,                NULL },
+   { "emubgra",   VIRGL_DEBUG_EMULATE_BGRA,        "Enable tweak to emulate BGRA as RGBA on GLES hosts"},
+   { "bgraswz",   VIRGL_DEBUG_BGRA_DEST_SWIZZLE,   "Enable tweak to swizzle emulated BGRA on GLES hosts" },
+   { "sync",      VIRGL_DEBUG_SYNC,                "Sync after every flush" },
+   { "xfer",      VIRGL_DEBUG_XFER,                "Do not optimize for transfers" },
    DEBUG_NAMED_VALUE_END
 };
 DEBUG_GET_ONCE_FLAGS_OPTION(virgl_debug, "VIRGL_DEBUG", debug_options, 0)
@@ -67,7 +71,9 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
    switch (param) {
    case PIPE_CAP_NPOT_TEXTURES:
       return 1;
-   case PIPE_CAP_SM3:
+   case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
+   case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
+   case PIPE_CAP_VERTEX_SHADER_SATURATE:
       return 1;
    case PIPE_CAP_ANISOTROPIC_FILTER:
       return 1;
@@ -872,6 +878,9 @@ virgl_create_screen(struct virgl_winsys *vws, const struct pipe_screen_config *c
             driQueryOptioni(config->options, VIRGL_GLES_SAMPLES_PASSED_VALUE);
    }
 
+   screen->tweak_gles_emulate_bgra |= !!(virgl_debug & VIRGL_DEBUG_EMULATE_BGRA);
+   screen->tweak_gles_apply_bgra_dest_swizzle |= !!(virgl_debug & VIRGL_DEBUG_BGRA_DEST_SWIZZLE);
+
    screen->vws = vws;
    screen->base.get_name = virgl_get_name;
    screen->base.get_vendor = virgl_get_vendor;