case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
return 0;
case PIPE_CAP_COMPUTE:
- return 0;
+ return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER;
case PIPE_CAP_USER_VERTEX_BUFFERS:
return 0;
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
return vscreen->caps.caps.v1.bset.transform_feedback_overflow_query;
case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
return vscreen->caps.caps.v2.shader_buffer_offset_alignment;
+ case PIPE_CAP_DOUBLES:
+ return vscreen->caps.caps.v1.bset.has_fp64;
+ case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
+ return vscreen->caps.caps.v2.max_shader_patch_varyings;
+ case PIPE_CAP_SAMPLER_VIEW_TARGET:
+ return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_VIEW;
+ case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
+ return vscreen->caps.caps.v2.max_vertex_attrib_stride;
+ case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
+ return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COPY_IMAGE;
+ case PIPE_CAP_TGSI_TXQS:
+ return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TXQS;
+ case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
+ return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FB_NO_ATTACH;
+ case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
+ return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_ROBUST_BUFFER_ACCESS;
case PIPE_CAP_TEXTURE_GATHER_SM5:
case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
case PIPE_CAP_FAKE_SW_MSAA:
case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
case PIPE_CAP_MULTI_DRAW_INDIRECT:
case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
- case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
- case PIPE_CAP_SAMPLER_VIEW_TARGET:
case PIPE_CAP_CLIP_HALFZ:
case PIPE_CAP_VERTEXID_NOBASE:
case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
- case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
case PIPE_CAP_DEPTH_BOUNDS_TEST:
- case PIPE_CAP_TGSI_TXQS:
case PIPE_CAP_SHAREABLE_SHADERS:
case PIPE_CAP_CLEAR_TEXTURE:
case PIPE_CAP_DRAW_PARAMETERS:
case PIPE_CAP_GENERATE_MIPMAP:
case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
case PIPE_CAP_QUERY_BUFFER_OBJECT:
- case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
case PIPE_CAP_STRING_MARKER:
case PIPE_CAP_QUERY_MEMORY_INFO:
case PIPE_CAP_PCI_GROUP:
case PIPE_CAP_PCI_BUS:
case PIPE_CAP_PCI_DEVICE:
case PIPE_CAP_PCI_FUNCTION:
- case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
- case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
case PIPE_CAP_TGSI_VOTE:
case PIPE_CAP_MAX_WINDOW_RECTANGLES:
case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
case PIPE_CAP_TGSI_BALLOT:
- case PIPE_CAP_DOUBLES:
case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
case PIPE_CAP_TILE_RASTER_ORDER:
case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
+ case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
case PIPE_CAP_CONTEXT_PRIORITY_MASK:
case PIPE_CAP_FENCE_SIGNAL:
case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
+ case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
return 0;
case PIPE_CAP_VENDOR_ID:
return 0x1af4;
enum pipe_shader_cap param)
{
struct virgl_screen *vscreen = virgl_screen(screen);
+
+ if ((shader == PIPE_SHADER_TESS_CTRL || shader == PIPE_SHADER_TESS_EVAL) &&
+ !vscreen->caps.caps.v1.bset.has_tessellation_shaders)
+ return 0;
+
+ if (shader == PIPE_SHADER_COMPUTE &&
+ !(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER))
+ return 0;
+
switch(shader)
{
case PIPE_SHADER_FRAGMENT:
case PIPE_SHADER_VERTEX:
case PIPE_SHADER_GEOMETRY:
+ case PIPE_SHADER_TESS_CTRL:
+ case PIPE_SHADER_TESS_EVAL:
+ case PIPE_SHADER_COMPUTE:
switch (param) {
case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
return 32;
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
return 4096 * sizeof(float[4]);
+ case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
+ if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
+ return vscreen->caps.caps.v2.max_shader_buffer_frag_compute;
+ else
+ return vscreen->caps.caps.v2.max_shader_buffer_other_stages;
+ case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
+ if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
+ return vscreen->caps.caps.v2.max_shader_image_frag_compute;
+ else
+ return vscreen->caps.caps.v2.max_shader_image_other_stages;
+ case PIPE_SHADER_CAP_SUPPORTED_IRS:
+ return (1 << PIPE_SHADER_IR_TGSI);
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
case PIPE_SHADER_CAP_INT64_ATOMICS:
case PIPE_SHADER_CAP_FP16:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
+ return 0;
+ case PIPE_SHADER_CAP_SCALAR_ISA:
+ return 1;
default:
return 0;
}
return 0.0;
}
+static int
+virgl_get_compute_param(struct pipe_screen *screen,
+ enum pipe_shader_ir ir_type,
+ enum pipe_compute_cap param,
+ void *ret)
+{
+ struct virgl_screen *vscreen = virgl_screen(screen);
+ if (!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER))
+ return 0;
+ switch (param) {
+ case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
+ if (ret) {
+ uint64_t *grid_size = ret;
+ grid_size[0] = vscreen->caps.caps.v2.max_compute_grid_size[0];
+ grid_size[1] = vscreen->caps.caps.v2.max_compute_grid_size[1];
+ grid_size[2] = vscreen->caps.caps.v2.max_compute_grid_size[2];
+ }
+ return 3 * sizeof(uint64_t) ;
+ case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
+ if (ret) {
+ uint64_t *block_size = ret;
+ block_size[0] = vscreen->caps.caps.v2.max_compute_block_size[0];
+ block_size[1] = vscreen->caps.caps.v2.max_compute_block_size[1];
+ block_size[2] = vscreen->caps.caps.v2.max_compute_block_size[2];
+ }
+ return 3 * sizeof(uint64_t);
+ case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
+ if (ret) {
+ uint64_t *max_threads_per_block = ret;
+ *max_threads_per_block = vscreen->caps.caps.v2.max_compute_work_group_invocations;
+ }
+ return sizeof(uint64_t);
+ case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
+ if (ret) {
+ uint64_t *max_local_size = ret;
+ /* Value reported by the closed source driver. */
+ *max_local_size = vscreen->caps.caps.v2.max_compute_shared_memory_size;
+ }
+ return sizeof(uint64_t);
+ default:
+ break;
+ }
+ return 0;
+}
+
static boolean
virgl_is_vertex_format_supported(struct pipe_screen *screen,
enum pipe_format format)
enum pipe_format format,
enum pipe_texture_target target,
unsigned sample_count,
+ unsigned storage_sample_count,
unsigned bind)
{
struct virgl_screen *vscreen = virgl_screen(screen);
const struct util_format_description *format_desc;
int i;
+ if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
+ return false;
+
assert(target == PIPE_BUFFER ||
target == PIPE_TEXTURE_1D ||
target == PIPE_TEXTURE_1D_ARRAY ||
if (sample_count > 1) {
if (!vscreen->caps.caps.v1.bset.texture_multisample)
return FALSE;
+
+ if (bind & PIPE_BIND_SHADER_IMAGE) {
+ if (sample_count > vscreen->caps.caps.v2.max_image_samples)
+ return FALSE;
+ }
+
if (sample_count > vscreen->caps.caps.v1.max_samples)
return FALSE;
}
return virgl_is_vertex_format_supported(screen, format);
}
+ /* Allow 3-comp 32 bit textures only for TBOs (needed for ARB_tbo_rgb32) */
+ if ((format == PIPE_FORMAT_R32G32B32_FLOAT ||
+ format == PIPE_FORMAT_R32G32B32_SINT ||
+ format == PIPE_FORMAT_R32G32B32_UINT) &&
+ target != PIPE_BUFFER)
+ return FALSE;
+
if (bind & PIPE_BIND_RENDER_TARGET) {
+ /* For ARB_framebuffer_no_attachments. */
+ if (format == PIPE_FORMAT_NONE)
+ return TRUE;
+
if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
return FALSE;
screen->base.get_vendor = virgl_get_vendor;
screen->base.get_param = virgl_get_param;
screen->base.get_shader_param = virgl_get_shader_param;
+ screen->base.get_compute_param = virgl_get_compute_param;
screen->base.get_paramf = virgl_get_paramf;
screen->base.is_format_supported = virgl_is_format_supported;
screen->base.destroy = virgl_destroy_screen;
projects / mesa.git / blobdiff