nouveau/nir: Implement load_global_constant

[mesa.git] / src / gallium / drivers / zink / zink_state.c

diff --git a/src/gallium/drivers/zink/zink_state.c b/src/gallium/drivers/zink/zink_state.c
index 07da1be2bf8ab1c763499f3beb99bd2c9a28d079..95f23c273ba39f7b02eb08d9fb0236526dcd08a3 100644 (file)
--- a/src/gallium/drivers/zink/zink_state.c
+++ b/src/gallium/drivers/zink/zink_state.c
@@ -35,6 +35,7 @@ zink_create_vertex_elements_state(struct pipe_context *pctx,
                                   unsigned num_elements,
                                   const struct pipe_vertex_element *elements)
 {
+   struct zink_screen *screen = zink_screen(pctx->screen);
    unsigned int i;
    struct zink_vertex_elements_state *ves = CALLOC_STRUCT(zink_vertex_elements_state);
    if (!ves)
@@ -62,7 +63,8 @@ zink_create_vertex_elements_state(struct pipe_context *pctx,
 
       ves->hw_state.attribs[i].binding = binding;
       ves->hw_state.attribs[i].location = i; // TODO: unsure
-      ves->hw_state.attribs[i].format = zink_get_format(elem->src_format);
+      ves->hw_state.attribs[i].format = zink_get_format(screen,
+                                                        elem->src_format);
       assert(ves->hw_state.attribs[i].format != VK_FORMAT_UNDEFINED);
       ves->hw_state.attribs[i].offset = elem->src_offset;
    }
@@ -79,6 +81,7 @@ zink_bind_vertex_elements_state(struct pipe_context *pctx,
    struct zink_context *ctx = zink_context(pctx);
    struct zink_gfx_pipeline_state *state = &ctx->gfx_pipeline_state;
    ctx->element_state = cso;
+   state->hash = 0;
    if (cso) {
       state->element_state = &ctx->element_state->hw_state;
       struct zink_vertex_elements_state *ves = cso;
@@ -254,7 +257,12 @@ zink_create_blend_state(struct pipe_context *pctx,
 static void
 zink_bind_blend_state(struct pipe_context *pctx, void *cso)
 {
-   zink_context(pctx)->gfx_pipeline_state.blend_state = cso;
+   struct zink_gfx_pipeline_state* state = &zink_context(pctx)->gfx_pipeline_state;
+
+   if (state->blend_state != cso) {
+      state->blend_state = cso;
+      state->hash = 0;
+   }
 }
 
 static void
@@ -346,7 +354,12 @@ zink_create_depth_stencil_alpha_state(struct pipe_context *pctx,
 static void
 zink_bind_depth_stencil_alpha_state(struct pipe_context *pctx, void *cso)
 {
-   zink_context(pctx)->gfx_pipeline_state.depth_stencil_alpha_state = cso;
+   struct zink_gfx_pipeline_state* state = &zink_context(pctx)->gfx_pipeline_state;
+
+   if (state->depth_stencil_alpha_state != cso) {
+      state->depth_stencil_alpha_state = cso;
+      state->hash = 0;
+   }
 }
 
 static void
@@ -420,8 +433,17 @@ zink_bind_rasterizer_state(struct pipe_context *pctx, void *cso)
    struct zink_context *ctx = zink_context(pctx);
    ctx->rast_state = cso;
 
-   if (ctx->rast_state)
-      ctx->gfx_pipeline_state.rast_state = &ctx->rast_state->hw_state;
+   if (ctx->rast_state) {
+      if (ctx->gfx_pipeline_state.rast_state != &ctx->rast_state->hw_state) {
+         ctx->gfx_pipeline_state.rast_state = &ctx->rast_state->hw_state;
+         ctx->gfx_pipeline_state.hash = 0;
+      }
+
+      if (ctx->line_width != ctx->rast_state->line_width) {
+         ctx->line_width = ctx->rast_state->line_width;
+         ctx->gfx_pipeline_state.hash = 0;
+      }
+   }
 }
 
 static void