radeonsi: move nir_shader_compiler_options into si_screen

[mesa.git] / src / gallium / frontends / vallium / val_execute.c

diff --git a/src/gallium/frontends/vallium/val_execute.c b/src/gallium/frontends/vallium/val_execute.c
index 16699bf3e1f2ac29d6275f2525c3e5d8446e4fe1..2415c010b74589a569217e11c3b7c28f31a3b711 100644 (file)
--- a/src/gallium/frontends/vallium/val_execute.c
+++ b/src/gallium/frontends/vallium/val_execute.c
@@ -837,8 +837,14 @@ static void fill_image_view_stage(struct rendering_state *state,
       state->iv[p_stage][idx].format = util_format_stencil_only(vk_format_to_pipe(iv->format));
    else
       state->iv[p_stage][idx].format = vk_format_to_pipe(iv->format);
-   state->iv[p_stage][idx].u.tex.first_layer = iv->subresourceRange.baseArrayLayer;
-   state->iv[p_stage][idx].u.tex.last_layer = iv->subresourceRange.baseArrayLayer + val_get_layerCount(iv->image, &iv->subresourceRange) - 1;
+
+   if (iv->view_type == VK_IMAGE_VIEW_TYPE_3D) {
+      state->iv[p_stage][idx].u.tex.first_layer = 0;
+      state->iv[p_stage][idx].u.tex.last_layer = u_minify(iv->image->bo->depth0, iv->subresourceRange.baseMipLevel) - 1;
+   } else {
+      state->iv[p_stage][idx].u.tex.first_layer = iv->subresourceRange.baseArrayLayer;
+      state->iv[p_stage][idx].u.tex.last_layer = iv->subresourceRange.baseArrayLayer + val_get_layerCount(iv->image, &iv->subresourceRange) - 1;
+   }
    state->iv[p_stage][idx].u.tex.level = iv->subresourceRange.baseMipLevel;
    if (state->num_shader_images[p_stage] <= idx)
       state->num_shader_images[p_stage] = idx + 1;