*/
PIPE_TRANSFER_MAP_DIRECTLY = (1 << 2),
- /**
- * The transfer should map the resource storage directly and the GPU should
- * be able to see what the CPU has written. Such a storage may stay mapped
- * while issuing draw commands which use it. The only allowed usage is
- * non-overlapping writes which are suballocated out of a big buffer.
- * The minimum allowed alignment of suballocations is 256 bytes (this is
- * a subject to change).
- * The flag is intended to be used to avoid mapping and unmapping
- * resources repeatedly when doing uploads and draws intermixed.
- *
- * The driver may return NULL if that isn't possible, and the state
- * tracker needs to cope with that and use an alternative path
- * without this flag.
- */
- PIPE_TRANSFER_MAP_PERMANENTLY = (1 << 3),
-
/**
* Discards the memory within the mapped region.
*
* - WDDM's D3DDDICB_LOCKFLAGS.IgnoreSync flag.
*/
PIPE_TRANSFER_UNSYNCHRONIZED = (1 << 10),
- PIPE_TRANSFER_NOOVERWRITE = (1 << 10), /* are these really the same?? */
/**
* Written ranges will be notified later with
#define PIPE_BIND_STREAM_OUTPUT (1 << 11) /* set_stream_output_buffers */
#define PIPE_BIND_CURSOR (1 << 16) /* mouse cursor */
#define PIPE_BIND_CUSTOM (1 << 17) /* state-tracker/winsys usages */
+#define PIPE_BIND_GLOBAL (1 << 18) /* set_global_binding */
+#define PIPE_BIND_SHADER_RESOURCE (1 << 19) /* set_shader_resources */
+#define PIPE_BIND_COMPUTE_RESOURCE (1 << 20) /* set_compute_resources */
/* The first two flags above were previously part of the amorphous
* TEXTURE_USAGE, most of which are now descriptions of the ways a
#define PIPE_SHADER_VERTEX 0
#define PIPE_SHADER_FRAGMENT 1
#define PIPE_SHADER_GEOMETRY 2
-#define PIPE_SHADER_TYPES 3
+#define PIPE_SHADER_COMPUTE 3
+#define PIPE_SHADER_TYPES 4
/**
enum pipe_cap {
PIPE_CAP_NPOT_TEXTURES = 1,
PIPE_CAP_TWO_SIDED_STENCIL = 2,
- PIPE_CAP_DUAL_SOURCE_BLEND = 4,
+ PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS = 4,
PIPE_CAP_ANISOTROPIC_FILTER = 5,
PIPE_CAP_POINT_SPRITE = 6,
PIPE_CAP_MAX_RENDER_TARGETS = 7,
PIPE_CAP_SHADER_STENCIL_EXPORT = 42,
PIPE_CAP_TGSI_INSTANCEID = 43,
PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR = 44,
- PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL = 45,
+ PIPE_CAP_FRAGMENT_COLOR_CLAMPED = 45,
PIPE_CAP_MIXED_COLORBUFFER_FORMATS = 46,
PIPE_CAP_SEAMLESS_CUBE_MAP = 47,
PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE = 48,
PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS = 56,
PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME = 57,
PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS = 58, /* temporary */
- PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS = 59 /* temporary */
+ PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS = 59, /* temporary */
+ PIPE_CAP_VERTEX_COLOR_UNCLAMPED = 60,
+ PIPE_CAP_VERTEX_COLOR_CLAMPED = 61,
+ PIPE_CAP_GLSL_FEATURE_LEVEL = 62,
+ PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION = 63,
+ PIPE_CAP_USER_VERTEX_BUFFERS = 64,
+ PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY = 65,
+ PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY = 66,
+ PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY = 67,
+ PIPE_CAP_COMPUTE = 68,
+ PIPE_CAP_USER_INDEX_BUFFERS = 69,
+ PIPE_CAP_USER_CONSTANT_BUFFERS = 70,
+ PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT = 71
};
/**
PIPE_SHADER_CAP_SUBROUTINES = 16, /* BGNSUB, ENDSUB, CAL, RET */
PIPE_SHADER_CAP_INTEGERS = 17,
PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS = 18,
- PIPE_SHADER_CAP_OUTPUT_READ = 19
+ PIPE_SHADER_CAP_PREFERRED_IR = 19
};
+/**
+ * Shader intermediate representation.
+ */
+enum pipe_shader_ir
+{
+ PIPE_SHADER_IR_TGSI
+};
+
+/**
+ * Compute-specific implementation capability. They can be queried
+ * using pipe_screen::get_compute_param.
+ */
+enum pipe_compute_cap
+{
+ PIPE_COMPUTE_CAP_GRID_DIMENSION,
+ PIPE_COMPUTE_CAP_MAX_GRID_SIZE,
+ PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE,
+ PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE,
+ PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE,
+ PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE,
+ PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
+};
/**
* Composite query types
*/
+
+/**
+ * Query result for PIPE_QUERY_SO_STATISTICS.
+ */
struct pipe_query_data_so_statistics
{
uint64_t num_primitives_written;
uint64_t primitives_storage_needed;
};
+
+/**
+ * Query result for PIPE_QUERY_TIMESTAMP_DISJOINT.
+ */
struct pipe_query_data_timestamp_disjoint
{
uint64_t frequency;
boolean disjoint;
};
+/**
+ * Query result for PIPE_QUERY_PIPELINE_STATISTICS.
+ */
+struct pipe_query_data_pipeline_statistics
+{
+ uint64_t ia_vertices; /**< Num vertices read by the vertex fetcher. */
+ uint64_t ia_primitives; /**< Num primitives read by the vertex fetcher. */
+ uint64_t vs_invocations; /**< Num vertex shader invocations. */
+ uint64_t gs_invocations; /**< Num geometry shader invocations. */
+ uint64_t gs_primitives; /**< Num primitives output by a geometry shader. */
+ uint64_t c_invocations; /**< Num primitives sent to the rasterizer. */
+ uint64_t c_primitives; /**< Num primitives that were rendered. */
+ uint64_t ps_invocations; /**< Num pixel shader invocations. */
+ uint64_t hs_invocations; /**< Num hull shader invocations. */
+ uint64_t ds_invocations; /**< Num domain shader invocations. */
+ uint64_t cs_invocations; /**< Num compute shader invocations. */
+};
+
+/**
+ * Query result (returned by pipe_context::get_query_result).
+ */
+union pipe_query_result
+{
+ /* PIPE_QUERY_OCCLUSION_PREDICATE */
+ /* PIPE_QUERY_SO_OVERFLOW_PREDICATE */
+ /* PIPE_QUERY_GPU_FINISHED */
+ boolean b;
+
+ /* PIPE_QUERY_OCCLUSION_COUNTER */
+ /* PIPE_QUERY_TIMESTAMP */
+ /* PIPE_QUERY_TIME_ELAPSED */
+ /* PIPE_QUERY_PRIMITIVES_GENERATED */
+ /* PIPE_QUERY_PRIMITIVES_EMITTED */
+ uint64_t u64;
+
+ /* PIPE_QUERY_SO_STATISTICS */
+ struct pipe_query_data_so_statistics so_statistics;
+
+ /* PIPE_QUERY_TIMESTAMP_DISJOINT */
+ struct pipe_query_data_timestamp_disjoint timestamp_disjoint;
+
+ /* PIPE_QUERY_PIPELINE_STATISTICS */
+ struct pipe_query_data_pipeline_statistics pipeline_statistics;
+};
+
union pipe_color_union
{
float f[4];