* PIPE_RESOURCE_FLAG_MAP_COHERENT must be set when creating
* the resource.
*/
- PIPE_TRANSFER_COHERENT = (1 << 14)
+ PIPE_TRANSFER_COHERENT = (1 << 14),
+
+ /**
+ * This and higher bits are reserved for private use by drivers. Drivers
+ * should use this as (PIPE_TRANSFER_DRV_PRV << i).
+ */
+ PIPE_TRANSFER_DRV_PRV = (1 << 24)
};
/**
*/
#define PIPE_CONTEXT_LOW_PRIORITY (1 << 5)
+/** Stop execution if the device is reset. */
+#define PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET (1 << 6)
+
/**
* Flags for pipe_context::memory_barrier.
*/
#define PIPE_BARRIER_FRAMEBUFFER (1 << 9)
#define PIPE_BARRIER_STREAMOUT_BUFFER (1 << 10)
#define PIPE_BARRIER_GLOBAL_BUFFER (1 << 11)
-#define PIPE_BARRIER_ALL ((1 << 12) - 1)
+#define PIPE_BARRIER_UPDATE_BUFFER (1 << 12)
+#define PIPE_BARRIER_UPDATE_TEXTURE (1 << 13)
+#define PIPE_BARRIER_ALL ((1 << 14) - 1)
+
+#define PIPE_BARRIER_UPDATE \
+ (PIPE_BARRIER_UPDATE_BUFFER | PIPE_BARRIER_UPDATE_TEXTURE)
/**
* Flags for pipe_context::texture_barrier.
#define PIPE_RESOURCE_FLAG_MAP_COHERENT (1 << 1)
#define PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY (1 << 2)
#define PIPE_RESOURCE_FLAG_SPARSE (1 << 3)
-#define PIPE_RESOURCE_FLAG_DRV_PRIV (1 << 16) /* driver/winsys private */
+#define PIPE_RESOURCE_FLAG_DRV_PRIV (1 << 8) /* driver/winsys private */
#define PIPE_RESOURCE_FLAG_ST_PRIV (1 << 24) /* state-tracker/winsys private */
/**
PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE,
PIPE_QUERY_GPU_FINISHED,
PIPE_QUERY_PIPELINE_STATISTICS,
+ PIPE_QUERY_PIPELINE_STATISTICS_SINGLE,
PIPE_QUERY_TYPES,
/* start of driver queries, see pipe_screen::get_driver_query_info */
PIPE_QUERY_DRIVER_SPECIFIC = 256,
};
+/**
+ * Index for PIPE_QUERY_PIPELINE_STATISTICS subqueries.
+ */
+enum pipe_statistics_query_index {
+ PIPE_STAT_QUERY_IA_VERTICES,
+ PIPE_STAT_QUERY_IA_PRIMITIVES,
+ PIPE_STAT_QUERY_VS_INVOCATIONS,
+ PIPE_STAT_QUERY_GS_INVOCATIONS,
+ PIPE_STAT_QUERY_GS_PRIMITIVES,
+ PIPE_STAT_QUERY_C_INVOCATIONS,
+ PIPE_STAT_QUERY_C_PRIMITIVES,
+ PIPE_STAT_QUERY_PS_INVOCATIONS,
+ PIPE_STAT_QUERY_HS_INVOCATIONS,
+ PIPE_STAT_QUERY_DS_INVOCATIONS,
+ PIPE_STAT_QUERY_CS_INVOCATIONS,
+};
+
/**
* Conditional rendering modes
*/
enum pipe_conservative_raster_mode
{
PIPE_CONSERVATIVE_RASTER_OFF,
+
+ /**
+ * The post-snap mode means the conservative rasterization occurs after
+ * the conversion from floating-point to fixed-point coordinates
+ * on the subpixel grid.
+ */
PIPE_CONSERVATIVE_RASTER_POST_SNAP,
+
+ /**
+ * The pre-snap mode means the conservative rasterization occurs before
+ * the conversion from floating-point to fixed-point coordinates.
+ */
PIPE_CONSERVATIVE_RASTER_PRE_SNAP,
};
* resource_get_handle flags.
*/
/* Requires pipe_context::flush_resource before external use. */
-#define PIPE_HANDLE_USAGE_EXPLICIT_FLUSH (1 << 0)
+#define PIPE_HANDLE_USAGE_EXPLICIT_FLUSH (1 << 0)
/* Expected external use of the resource: */
-#define PIPE_HANDLE_USAGE_READ (1 << 1)
-#define PIPE_HANDLE_USAGE_WRITE (1 << 2)
-#define PIPE_HANDLE_USAGE_READ_WRITE (PIPE_HANDLE_USAGE_READ | \
- PIPE_HANDLE_USAGE_WRITE)
+#define PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE (1 << 1)
+#define PIPE_HANDLE_USAGE_SHADER_WRITE (1 << 2)
/**
* pipe_image_view access flags.
PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER,
PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER,
PIPE_CAP_DEPTH_CLIP_DISABLE,
+ PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE,
PIPE_CAP_SHADER_STENCIL_EXPORT,
PIPE_CAP_TGSI_INSTANCEID,
PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR,
PIPE_CAP_VERTEX_COLOR_CLAMPED,
PIPE_CAP_GLSL_FEATURE_LEVEL,
PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY,
+ PIPE_CAP_ESSL_FEATURE_LEVEL,
PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION,
PIPE_CAP_USER_VERTEX_BUFFERS,
PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY,
PIPE_CAP_TGSI_CAN_READ_OUTPUTS,
PIPE_CAP_NATIVE_FENCE_FD,
PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY,
+ PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS,
PIPE_CAP_TGSI_FS_FBFETCH,
PIPE_CAP_TGSI_MUL_ZERO_WINS,
PIPE_CAP_DOUBLES,
PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES,
PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS,
PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE,
+ PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE,
PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS,
PIPE_CAP_MAX_GS_INVOCATIONS,
PIPE_CAP_MAX_SHADER_BUFFER_SIZE,
PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS,
PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS,
PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS,
+ PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET,
+ PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET,
+ PIPE_CAP_SURFACE_SAMPLE_COUNT,
+ PIPE_CAP_TGSI_ATOMFADD,
+ PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE,
+ PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND,
+ PIPE_CAP_DEST_SURFACE_SRGB_CONTROL,
+ PIPE_CAP_NIR_COMPACT_ARRAYS,
+ PIPE_CAP_MAX_VARYINGS,
+ PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK,
+ PIPE_CAP_COMPUTE_SHADER_DERIVATIVES,
+ PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS,
+ PIPE_CAP_IMAGE_LOAD_FORMATTED,
};
/**
PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK,
};
+/**
+ * Types of parameters for pipe_context::set_context_param.
+ */
+enum pipe_context_param
+{
+ /* A hint for the driver that it should pin its execution threads to
+ * a group of cores sharing a specific L3 cache if the CPU has multiple
+ * L3 caches. This is needed for good multithreading performance on
+ * AMD Zen CPUs. "value" is the L3 cache index. Drivers that don't have
+ * any internal threads or don't run on affected CPUs can ignore this.
+ */
+ PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE,
+};
+
/**
* Composite query types
*/