PIPE_POLYGON_MODE_FILL,
PIPE_POLYGON_MODE_LINE,
PIPE_POLYGON_MODE_POINT,
+ PIPE_POLYGON_MODE_FILL_RECTANGLE,
};
/** Polygon face specification, eg for culling */
{
PIPE_FLUSH_END_OF_FRAME = (1 << 0),
PIPE_FLUSH_DEFERRED = (1 << 1),
+ PIPE_FLUSH_FENCE_FD = (1 << 2),
};
/**
#define PIPE_BARRIER_GLOBAL_BUFFER (1 << 11)
#define PIPE_BARRIER_ALL ((1 << 12) - 1)
+/**
+ * Flags for pipe_context::texture_barrier.
+ */
+#define PIPE_TEXTURE_BARRIER_SAMPLER (1 << 0)
+#define PIPE_TEXTURE_BARRIER_FRAMEBUFFER (1 << 1)
+
/**
* Resource binding flags -- state tracker must specify in advance all
* the ways a resource might be used.
*/
#define PIPE_RESOURCE_FLAG_MAP_PERSISTENT (1 << 0)
#define PIPE_RESOURCE_FLAG_MAP_COHERENT (1 << 1)
+#define PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY (1 << 2)
+#define PIPE_RESOURCE_FLAG_SPARSE (1 << 3)
#define PIPE_RESOURCE_FLAG_DRV_PRIV (1 << 16) /* driver/winsys private */
#define PIPE_RESOURCE_FLAG_ST_PRIV (1 << 24) /* state-tracker/winsys private */
PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY,
PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY,
PIPE_CAP_COMPUTE,
- PIPE_CAP_USER_INDEX_BUFFERS,
PIPE_CAP_USER_CONSTANT_BUFFERS,
PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT,
PIPE_CAP_START_INSTANCE,
PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED,
PIPE_CAP_VIEWPORT_SUBPIXEL_BITS,
PIPE_CAP_MIXED_COLOR_DEPTH_BITS,
+ PIPE_CAP_TGSI_ARRAY_COMPONENTS,
+ PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS,
+ PIPE_CAP_TGSI_CAN_READ_OUTPUTS,
+ PIPE_CAP_NATIVE_FENCE_FD,
+ PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY,
+ PIPE_CAP_TGSI_FS_FBFETCH,
+ PIPE_CAP_TGSI_MUL_ZERO_WINS,
+ PIPE_CAP_DOUBLES,
+ PIPE_CAP_INT64,
+ PIPE_CAP_INT64_DIVMOD,
+ PIPE_CAP_TGSI_TEX_TXF_LZ,
+ PIPE_CAP_TGSI_CLOCK,
+ PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE,
+ PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE,
+ PIPE_CAP_TGSI_BALLOT,
+ PIPE_CAP_TGSI_TES_LAYER_VIEWPORT,
};
#define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50 (1 << 0)
PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE,
PIPE_SHADER_CAP_MAX_CONST_BUFFERS,
PIPE_SHADER_CAP_MAX_TEMPS,
- PIPE_SHADER_CAP_MAX_PREDS,
/* boolean caps */
PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED,
PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR,
PIPE_SHADER_CAP_PREFERRED_IR,
PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED,
PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS,
- PIPE_SHADER_CAP_DOUBLES,
PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED, /* all rounding modes */
PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED,
PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED,
PIPE_SHADER_CAP_MAX_SHADER_BUFFERS,
PIPE_SHADER_CAP_SUPPORTED_IRS,
PIPE_SHADER_CAP_MAX_SHADER_IMAGES,
+ PIPE_SHADER_CAP_LOWER_IF_THRESHOLD,
+ PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS,
};
/**