winsys/amdgpu: enable buffer allocation from slabs

[mesa.git] / src / gallium / winsys / amdgpu / drm / amdgpu_bo.c

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index c367929b5be1a7f9c3d988d7c10f56781f8cc5de..c13dc2b0e90a63b9a0476d85f76f1846d622e3f9 100644 (file)
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -38,6 +38,13 @@
 #include <stdio.h>
 #include <inttypes.h>
 
+static struct pb_buffer *
+amdgpu_bo_create(struct radeon_winsys *rws,
+                 uint64_t size,
+                 unsigned alignment,
+                 enum radeon_bo_domain domain,
+                 enum radeon_bo_flag flags);
+
 static bool amdgpu_bo_wait(struct pb_buffer *_buf, uint64_t timeout,
                            enum radeon_bo_usage usage)
 {
@@ -443,6 +450,116 @@ bool amdgpu_bo_can_reclaim(struct pb_buffer *_buf)
    return amdgpu_bo_wait(_buf, 0, RADEON_USAGE_READWRITE);
 }
 
+bool amdgpu_bo_can_reclaim_slab(void *priv, struct pb_slab_entry *entry)
+{
+   struct amdgpu_winsys_bo *bo = NULL; /* fix container_of */
+   bo = container_of(entry, bo, u.slab.entry);
+
+   return amdgpu_bo_can_reclaim(&bo->base);
+}
+
+static void amdgpu_bo_slab_destroy(struct pb_buffer *_buf)
+{
+   struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);
+
+   assert(!bo->bo);
+
+   pb_slab_free(&bo->ws->bo_slabs, &bo->u.slab.entry);
+}
+
+static const struct pb_vtbl amdgpu_winsys_bo_slab_vtbl = {
+   amdgpu_bo_slab_destroy
+   /* other functions are never called */
+};
+
+struct pb_slab *amdgpu_bo_slab_alloc(void *priv, unsigned heap,
+                                     unsigned entry_size,
+                                     unsigned group_index)
+{
+   struct amdgpu_winsys *ws = priv;
+   struct amdgpu_slab *slab = CALLOC_STRUCT(amdgpu_slab);
+   enum radeon_bo_domain domains;
+   enum radeon_bo_flag flags = 0;
+   uint32_t base_id;
+
+   if (!slab)
+      return NULL;
+
+   if (heap & 1)
+      flags |= RADEON_FLAG_GTT_WC;
+   if (heap & 2)
+      flags |= RADEON_FLAG_CPU_ACCESS;
+
+   switch (heap >> 2) {
+   case 0:
+      domains = RADEON_DOMAIN_VRAM;
+      break;
+   default:
+   case 1:
+      domains = RADEON_DOMAIN_VRAM_GTT;
+      break;
+   case 2:
+      domains = RADEON_DOMAIN_GTT;
+      break;
+   }
+
+   slab->buffer = amdgpu_winsys_bo(amdgpu_bo_create(&ws->base,
+                                                    64 * 1024, 64 * 1024,
+                                                    domains, flags));
+   if (!slab->buffer)
+      goto fail;
+
+   assert(slab->buffer->bo);
+
+   slab->base.num_entries = slab->buffer->base.size / entry_size;
+   slab->base.num_free = slab->base.num_entries;
+   slab->entries = CALLOC(slab->base.num_entries, sizeof(*slab->entries));
+   if (!slab->entries)
+      goto fail_buffer;
+
+   LIST_INITHEAD(&slab->base.free);
+
+   base_id = __sync_fetch_and_add(&ws->next_bo_unique_id, slab->base.num_entries);
+
+   for (unsigned i = 0; i < slab->base.num_entries; ++i) {
+      struct amdgpu_winsys_bo *bo = &slab->entries[i];
+
+      bo->base.alignment = entry_size;
+      bo->base.usage = slab->buffer->base.usage;
+      bo->base.size = entry_size;
+      bo->base.vtbl = &amdgpu_winsys_bo_slab_vtbl;
+      bo->ws = ws;
+      bo->va = slab->buffer->va + i * entry_size;
+      bo->initial_domain = domains;
+      bo->unique_id = base_id + i;
+      bo->u.slab.entry.slab = &slab->base;
+      bo->u.slab.entry.group_index = group_index;
+      bo->u.slab.real = slab->buffer;
+
+      LIST_ADDTAIL(&bo->u.slab.entry.head, &slab->base.free);
+   }
+
+   return &slab->base;
+
+fail_buffer:
+   amdgpu_winsys_bo_reference(&slab->buffer, NULL);
+fail:
+   FREE(slab);
+   return NULL;
+}
+
+void amdgpu_bo_slab_free(void *priv, struct pb_slab *pslab)
+{
+   struct amdgpu_slab *slab = amdgpu_slab(pslab);
+
+   for (unsigned i = 0; i < slab->base.num_entries; ++i)
+      amdgpu_bo_remove_fences(&slab->entries[i]);
+
+   FREE(slab->entries);
+   amdgpu_winsys_bo_reference(&slab->buffer, NULL);
+   FREE(slab);
+}
+
 static unsigned eg_tile_split(unsigned tile_split)
 {
    switch (tile_split) {
@@ -555,6 +672,53 @@ amdgpu_bo_create(struct radeon_winsys *rws,
    struct amdgpu_winsys_bo *bo;
    unsigned usage = 0, pb_cache_bucket;
 
+   /* Sub-allocate small buffers from slabs. */
+   if (!(flags & RADEON_FLAG_HANDLE) &&
+       size <= (1 << AMDGPU_SLAB_MAX_SIZE_LOG2) &&
+       alignment <= MAX2(1 << AMDGPU_SLAB_MIN_SIZE_LOG2, util_next_power_of_two(size))) {
+      struct pb_slab_entry *entry;
+      unsigned heap = 0;
+
+      if (flags & RADEON_FLAG_GTT_WC)
+         heap |= 1;
+      if (flags & RADEON_FLAG_CPU_ACCESS)
+         heap |= 2;
+      if (flags & ~(RADEON_FLAG_GTT_WC | RADEON_FLAG_CPU_ACCESS))
+         goto no_slab;
+
+      switch (domain) {
+      case RADEON_DOMAIN_VRAM:
+         heap |= 0 * 4;
+         break;
+      case RADEON_DOMAIN_VRAM_GTT:
+         heap |= 1 * 4;
+         break;
+      case RADEON_DOMAIN_GTT:
+         heap |= 2 * 4;
+         break;
+      default:
+         goto no_slab;
+      }
+
+      entry = pb_slab_alloc(&ws->bo_slabs, size, heap);
+      if (!entry) {
+         /* Clear the cache and try again. */
+         pb_cache_release_all_buffers(&ws->bo_cache);
+
+         entry = pb_slab_alloc(&ws->bo_slabs, size, heap);
+      }
+      if (!entry)
+         return NULL;
+
+      bo = NULL;
+      bo = container_of(entry, bo, u.slab.entry);
+
+      pipe_reference_init(&bo->base.reference, 1);
+
+      return &bo->base;
+   }
+no_slab:
+
    /* This flag is irrelevant for the cache. */
    flags &= ~RADEON_FLAG_HANDLE;
 
@@ -597,6 +761,7 @@ amdgpu_bo_create(struct radeon_winsys *rws,
                          pb_cache_bucket);
    if (!bo) {
       /* Clear the cache and try again. */
+      pb_slabs_reclaim(&ws->bo_slabs);
       pb_cache_release_all_buffers(&ws->bo_cache);
       bo = amdgpu_create_bo(ws, size, alignment, usage, domain, flags,
                             pb_cache_bucket);