return &cs->const_preamble_ib.base;
}
-#define OUT_CS(cs, value) (cs)->current.buf[(cs)->current.cdw++] = (value)
-
static int amdgpu_cs_lookup_buffer(struct radeon_winsys_cs *rcs,
struct pb_buffer *buf)
{
/* Pad with NOPs and add INDIRECT_BUFFER packet */
while ((rcs->current.cdw & 7) != 4)
- OUT_CS(rcs, 0xffff1000); /* type3 nop packet */
+ radeon_emit(rcs, 0xffff1000); /* type3 nop packet */
- OUT_CS(rcs, PKT3(ib->ib_type == IB_MAIN ? PKT3_INDIRECT_BUFFER_CIK
+ radeon_emit(rcs, PKT3(ib->ib_type == IB_MAIN ? PKT3_INDIRECT_BUFFER_CIK
: PKT3_INDIRECT_BUFFER_CONST, 2, 0));
- OUT_CS(rcs, va);
- OUT_CS(rcs, va >> 32);
+ radeon_emit(rcs, va);
+ radeon_emit(rcs, va >> 32);
new_ptr_ib_size = &rcs->current.buf[rcs->current.cdw];
- OUT_CS(rcs, S_3F2_CHAIN(1) | S_3F2_VALID(1));
+ radeon_emit(rcs, S_3F2_CHAIN(1) | S_3F2_VALID(1));
assert((rcs->current.cdw & 7) == 0);
assert(rcs->current.cdw <= rcs->current.max_dw);
static void amdgpu_add_fence_dependencies(struct amdgpu_cs *acs)
{
struct amdgpu_cs_context *cs = acs->csc;
- int i, j;
+ int i;
cs->request.number_of_dependencies = 0;
for (i = 0; i < cs->num_buffers; i++) {
- for (j = 0; j < RING_LAST; j++) {
- struct amdgpu_cs_fence *dep;
- unsigned idx;
-
- struct amdgpu_fence *bo_fence = (void *)cs->buffers[i].bo->fence[j];
- if (!bo_fence)
- continue;
-
- if (bo_fence->ctx == acs->ctx &&
- bo_fence->fence.ip_type == cs->request.ip_type &&
- bo_fence->fence.ip_instance == cs->request.ip_instance &&
- bo_fence->fence.ring == cs->request.ring)
- continue;
-
- if (amdgpu_fence_wait((void *)bo_fence, 0, false))
- continue;
-
- if (bo_fence->submission_in_progress)
- os_wait_until_zero(&bo_fence->submission_in_progress,
- PIPE_TIMEOUT_INFINITE);
-
- idx = cs->request.number_of_dependencies++;
- if (idx >= cs->max_dependencies) {
- unsigned size;
-
- cs->max_dependencies = idx + 8;
- size = cs->max_dependencies * sizeof(struct amdgpu_cs_fence);
- cs->request.dependencies = realloc(cs->request.dependencies, size);
- }
-
- dep = &cs->request.dependencies[idx];
- memcpy(dep, &bo_fence->fence, sizeof(*dep));
+ struct amdgpu_cs_fence *dep;
+ unsigned idx;
+
+ struct amdgpu_fence *bo_fence = (void *)cs->buffers[i].bo->fence;
+ if (!bo_fence)
+ continue;
+
+ if (bo_fence->ctx == acs->ctx &&
+ bo_fence->fence.ip_type == cs->request.ip_type &&
+ bo_fence->fence.ip_instance == cs->request.ip_instance &&
+ bo_fence->fence.ring == cs->request.ring)
+ continue;
+
+ if (amdgpu_fence_wait((void *)bo_fence, 0, false))
+ continue;
+
+ if (bo_fence->submission_in_progress)
+ os_wait_until_zero(&bo_fence->submission_in_progress,
+ PIPE_TIMEOUT_INFINITE);
+
+ idx = cs->request.number_of_dependencies++;
+ if (idx >= cs->max_dependencies) {
+ unsigned size;
+
+ cs->max_dependencies = idx + 8;
+ size = cs->max_dependencies * sizeof(struct amdgpu_cs_fence);
+ cs->request.dependencies = realloc(cs->request.dependencies, size);
}
+
+ dep = &cs->request.dependencies[idx];
+ memcpy(dep, &bo_fence->fence, sizeof(*dep));
}
}
/* pad DMA ring to 8 DWs */
if (ws->info.chip_class <= SI) {
while (rcs->current.cdw & 7)
- OUT_CS(rcs, 0xf0000000); /* NOP packet */
+ radeon_emit(rcs, 0xf0000000); /* NOP packet */
} else {
while (rcs->current.cdw & 7)
- OUT_CS(rcs, 0x00000000); /* NOP packet */
+ radeon_emit(rcs, 0x00000000); /* NOP packet */
}
break;
case RING_GFX:
/* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
if (ws->info.gfx_ib_pad_with_type2) {
while (rcs->current.cdw & 7)
- OUT_CS(rcs, 0x80000000); /* type2 nop packet */
+ radeon_emit(rcs, 0x80000000); /* type2 nop packet */
} else {
while (rcs->current.cdw & 7)
- OUT_CS(rcs, 0xffff1000); /* type3 nop packet */
+ radeon_emit(rcs, 0xffff1000); /* type3 nop packet */
}
/* Also pad the const IB. */
if (cs->const_ib.ib_mapped)
while (!cs->const_ib.base.current.cdw || (cs->const_ib.base.current.cdw & 7))
- OUT_CS(&cs->const_ib.base, 0xffff1000); /* type3 nop packet */
+ radeon_emit(&cs->const_ib.base, 0xffff1000); /* type3 nop packet */
if (cs->const_preamble_ib.ib_mapped)
while (!cs->const_preamble_ib.base.current.cdw || (cs->const_preamble_ib.base.current.cdw & 7))
- OUT_CS(&cs->const_preamble_ib.base, 0xffff1000);
+ radeon_emit(&cs->const_preamble_ib.base, 0xffff1000);
break;
case RING_UVD:
while (rcs->current.cdw & 15)
- OUT_CS(rcs, 0x80000000); /* type2 nop packet */
+ radeon_emit(rcs, 0x80000000); /* type2 nop packet */
break;
default:
break;
amdgpu_add_fence_dependencies(cs);
for (i = 0; i < num_buffers; i++) {
p_atomic_inc(&cur->buffers[i].bo->num_active_ioctls);
- amdgpu_fence_reference(&cur->buffers[i].bo->fence[cs->ring_type],
+ amdgpu_fence_reference(&cur->buffers[i].bo->fence,
cur->fence);
}
pipe_mutex_unlock(ws->bo_fence_lock);