Treewide: Remove Elements() macro

[mesa.git] / src / gallium / winsys / amdgpu / drm / amdgpu_cs.c

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 69fb9bb4f9d7d70bc16fcaa14ad37e58eb852c3f..29692cdb0355e8ad94bc375b79e7c35befc2b577 100644 (file)
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -138,8 +138,8 @@ static struct radeon_winsys_ctx *amdgpu_ctx_create(struct radeon_winsys *ws)
       return NULL;
    }
 
-   alloc_buffer.alloc_size = 4 * 1024;
-   alloc_buffer.phys_alignment = 4 *1024;
+   alloc_buffer.alloc_size = ctx->ws->info.gart_page_size;
+   alloc_buffer.phys_alignment = ctx->ws->info.gart_page_size;
    alloc_buffer.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
 
    r = amdgpu_bo_alloc(ctx->ws->dev, &alloc_buffer, &buf_handle);
@@ -201,6 +201,7 @@ amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx *rwctx)
 static bool amdgpu_get_new_ib(struct radeon_winsys *ws, struct amdgpu_ib *ib,
                               struct amdgpu_cs_ib_info *info, unsigned ib_type)
 {
+   struct amdgpu_winsys *aws = (struct amdgpu_winsys*)ws;
    /* Small IBs are better than big IBs, because the GPU goes idle quicker
     * and there is less waiting for buffers and fences. Proof:
     *   http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
@@ -236,7 +237,7 @@ static bool amdgpu_get_new_ib(struct radeon_winsys *ws, struct amdgpu_ib *ib,
       ib->used_ib_space = 0;
 
       ib->big_ib_buffer = ws->buffer_create(ws, buffer_size,
-                                            4096, true,
+                                            aws->info.gart_page_size,
                                             RADEON_DOMAIN_GTT,
                                             RADEON_FLAG_CPU_ACCESS);
       if (!ib->big_ib_buffer)
@@ -305,7 +306,7 @@ static boolean amdgpu_init_cs_context(struct amdgpu_cs *cs,
       return FALSE;
    }
 
-   for (i = 0; i < Elements(cs->buffer_indices_hashlist); i++) {
+   for (i = 0; i < ARRAY_SIZE(cs->buffer_indices_hashlist); i++) {
       cs->buffer_indices_hashlist[i] = -1;
    }
    return TRUE;
@@ -326,7 +327,7 @@ static void amdgpu_cs_context_cleanup(struct amdgpu_cs *cs)
    cs->used_gart = 0;
    cs->used_vram = 0;
 
-   for (i = 0; i < Elements(cs->buffer_indices_hashlist); i++) {
+   for (i = 0; i < ARRAY_SIZE(cs->buffer_indices_hashlist); i++) {
       cs->buffer_indices_hashlist[i] = -1;
    }
 }
@@ -426,7 +427,7 @@ amdgpu_cs_add_const_preamble_ib(struct radeon_winsys_cs *rcs)
 
 int amdgpu_lookup_buffer(struct amdgpu_cs *cs, struct amdgpu_winsys_bo *bo)
 {
-   unsigned hash = bo->unique_id & (Elements(cs->buffer_indices_hashlist)-1);
+   unsigned hash = bo->unique_id & (ARRAY_SIZE(cs->buffer_indices_hashlist)-1);
    int i = cs->buffer_indices_hashlist[hash];
 
    /* not found or found */
@@ -460,7 +461,7 @@ static unsigned amdgpu_add_buffer(struct amdgpu_cs *cs,
                                  enum radeon_bo_domain *added_domains)
 {
    struct amdgpu_cs_buffer *buffer;
-   unsigned hash = bo->unique_id & (Elements(cs->buffer_indices_hashlist)-1);
+   unsigned hash = bo->unique_id & (ARRAY_SIZE(cs->buffer_indices_hashlist)-1);
    int i = -1;
 
    assert(priority < 64);
@@ -525,10 +526,10 @@ static unsigned amdgpu_cs_add_buffer(struct radeon_winsys_cs *rcs,
    unsigned index = amdgpu_add_buffer(cs, bo, usage, bo->initial_domain,
                                      priority, &added_domains);
 
-   if (added_domains & RADEON_DOMAIN_GTT)
-      cs->used_gart += bo->base.size;
    if (added_domains & RADEON_DOMAIN_VRAM)
       cs->used_vram += bo->base.size;
+   else if (added_domains & RADEON_DOMAIN_GTT)
+      cs->used_gart += bo->base.size;
 
    return index;
 }
@@ -549,11 +550,24 @@ static boolean amdgpu_cs_validate(struct radeon_winsys_cs *rcs)
 static boolean amdgpu_cs_memory_below_limit(struct radeon_winsys_cs *rcs, uint64_t vram, uint64_t gtt)
 {
    struct amdgpu_cs *cs = amdgpu_cs(rcs);
-   boolean status =
-         (cs->used_gart + gtt) < cs->ctx->ws->info.gart_size * 0.7 &&
-         (cs->used_vram + vram) < cs->ctx->ws->info.vram_size * 0.7;
+   struct amdgpu_winsys *ws = cs->ctx->ws;
+
+   vram += cs->used_vram;
+   gtt += cs->used_gart;
+
+   /* Anything that goes above the VRAM size should go to GTT. */
+   if (vram > ws->info.vram_size)
+       gtt += vram - ws->info.vram_size;
+
+   /* Now we just need to check if we have enough GTT. */
+   return gtt < ws->info.gart_size * 0.7;
+}
+
+static uint64_t amdgpu_cs_query_memory_usage(struct radeon_winsys_cs *rcs)
+{
+   struct amdgpu_cs *cs = amdgpu_cs(rcs);
 
-   return status;
+   return cs->used_vram + cs->used_gart;
 }
 
 static unsigned amdgpu_cs_get_buffer_list(struct radeon_winsys_cs *rcs,
@@ -821,6 +835,7 @@ void amdgpu_cs_init_functions(struct amdgpu_winsys *ws)
    ws->base.cs_lookup_buffer = amdgpu_cs_lookup_buffer;
    ws->base.cs_validate = amdgpu_cs_validate;
    ws->base.cs_memory_below_limit = amdgpu_cs_memory_below_limit;
+   ws->base.cs_query_memory_usage = amdgpu_cs_query_memory_usage;
    ws->base.cs_get_buffer_list = amdgpu_cs_get_buffer_list;
    ws->base.cs_flush = amdgpu_cs_flush;
    ws->base.cs_is_buffer_referenced = amdgpu_bo_is_referenced;