#include <stdio.h>
#include <amdgpu_drm.h>
+#include "../../../drivers/radeonsi/sid.h"
/* FENCES */
/* COMMAND SUBMISSION */
-static bool amdgpu_get_new_ib(struct radeon_winsys *ws, struct amdgpu_ib *ib,
- struct amdgpu_cs_ib_info *info, unsigned ib_type)
+static bool amdgpu_cs_has_user_fence(struct amdgpu_cs_context *cs)
+{
+ return cs->request.ip_type != AMDGPU_HW_IP_UVD &&
+ cs->request.ip_type != AMDGPU_HW_IP_VCE;
+}
+
+static bool amdgpu_cs_has_chaining(enum ring_type ring_type)
+{
+ return ring_type == RING_GFX;
+}
+
+static unsigned amdgpu_cs_epilog_dws(enum ring_type ring_type)
+{
+ if (ring_type == RING_GFX)
+ return 4; /* for chaining */
+
+ return 0;
+}
+
+int amdgpu_lookup_buffer(struct amdgpu_cs_context *cs, struct amdgpu_winsys_bo *bo)
+{
+ unsigned hash = bo->unique_id & (ARRAY_SIZE(cs->buffer_indices_hashlist)-1);
+ int i = cs->buffer_indices_hashlist[hash];
+
+ /* not found or found */
+ if (i == -1 || cs->buffers[i].bo == bo)
+ return i;
+
+ /* Hash collision, look for the BO in the list of buffers linearly. */
+ for (i = cs->num_buffers - 1; i >= 0; i--) {
+ if (cs->buffers[i].bo == bo) {
+ /* Put this buffer in the hash list.
+ * This will prevent additional hash collisions if there are
+ * several consecutive lookup_buffer calls for the same buffer.
+ *
+ * Example: Assuming buffers A,B,C collide in the hash list,
+ * the following sequence of buffers:
+ * AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
+ * will collide here: ^ and here: ^,
+ * meaning that we should get very few collisions in the end. */
+ cs->buffer_indices_hashlist[hash] = i;
+ return i;
+ }
+ }
+ return -1;
+}
+
+static unsigned amdgpu_add_buffer(struct amdgpu_cs *acs,
+ struct amdgpu_winsys_bo *bo,
+ enum radeon_bo_usage usage,
+ enum radeon_bo_domain domains,
+ unsigned priority,
+ enum radeon_bo_domain *added_domains)
+{
+ struct amdgpu_cs_context *cs = acs->csc;
+ struct amdgpu_cs_buffer *buffer;
+ unsigned hash = bo->unique_id & (ARRAY_SIZE(cs->buffer_indices_hashlist)-1);
+ int i = -1;
+
+ assert(priority < 64);
+ *added_domains = 0;
+
+ i = amdgpu_lookup_buffer(cs, bo);
+
+ if (i >= 0) {
+ buffer = &cs->buffers[i];
+ buffer->priority_usage |= 1llu << priority;
+ buffer->usage |= usage;
+ *added_domains = domains & ~buffer->domains;
+ buffer->domains |= domains;
+ cs->flags[i] = MAX2(cs->flags[i], priority / 4);
+ return i;
+ }
+
+ /* New buffer, check if the backing array is large enough. */
+ if (cs->num_buffers >= cs->max_num_buffers) {
+ uint32_t size;
+ cs->max_num_buffers += 10;
+
+ size = cs->max_num_buffers * sizeof(struct amdgpu_cs_buffer);
+ cs->buffers = realloc(cs->buffers, size);
+
+ size = cs->max_num_buffers * sizeof(amdgpu_bo_handle);
+ cs->handles = realloc(cs->handles, size);
+
+ cs->flags = realloc(cs->flags, cs->max_num_buffers);
+ }
+
+ /* Initialize the new buffer. */
+ cs->buffers[cs->num_buffers].bo = NULL;
+ amdgpu_winsys_bo_reference(&cs->buffers[cs->num_buffers].bo, bo);
+ cs->handles[cs->num_buffers] = bo->bo;
+ cs->flags[cs->num_buffers] = priority / 4;
+ p_atomic_inc(&bo->num_cs_references);
+ buffer = &cs->buffers[cs->num_buffers];
+ buffer->bo = bo;
+ buffer->priority_usage = 1llu << priority;
+ buffer->usage = usage;
+ buffer->domains = domains;
+
+ cs->buffer_indices_hashlist[hash] = cs->num_buffers;
+
+ *added_domains = domains;
+ return cs->num_buffers++;
+}
+
+static unsigned amdgpu_cs_add_buffer(struct radeon_winsys_cs *rcs,
+ struct pb_buffer *buf,
+ enum radeon_bo_usage usage,
+ enum radeon_bo_domain domains,
+ enum radeon_bo_priority priority)
+{
+ /* Don't use the "domains" parameter. Amdgpu doesn't support changing
+ * the buffer placement during command submission.
+ */
+ struct amdgpu_cs *cs = amdgpu_cs(rcs);
+ struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)buf;
+ enum radeon_bo_domain added_domains;
+ unsigned index = amdgpu_add_buffer(cs, bo, usage, bo->initial_domain,
+ priority, &added_domains);
+
+ if (added_domains & RADEON_DOMAIN_VRAM)
+ cs->csc->used_vram += bo->base.size;
+ else if (added_domains & RADEON_DOMAIN_GTT)
+ cs->csc->used_gart += bo->base.size;
+
+ return index;
+}
+
+static bool amdgpu_ib_new_buffer(struct amdgpu_winsys *ws, struct amdgpu_ib *ib)
+{
+ struct pb_buffer *pb;
+ uint8_t *mapped;
+ unsigned buffer_size;
+
+ /* Always create a buffer that is at least as large as the maximum seen IB
+ * size, aligned to a power of two (and multiplied by 4 to reduce internal
+ * fragmentation if chaining is not available). Limit to 512k dwords, which
+ * is the largest power of two that fits into the size field of the
+ * INDIRECT_BUFFER packet.
+ */
+ if (amdgpu_cs_has_chaining(amdgpu_cs_from_ib(ib)->ring_type))
+ buffer_size = 4 *util_next_power_of_two(ib->max_ib_size);
+ else
+ buffer_size = 4 *util_next_power_of_two(4 * ib->max_ib_size);
+
+ buffer_size = MIN2(buffer_size, 4 * 512 * 1024);
+
+ switch (ib->ib_type) {
+ case IB_CONST_PREAMBLE:
+ buffer_size = MAX2(buffer_size, 4 * 1024);
+ break;
+ case IB_CONST:
+ buffer_size = MAX2(buffer_size, 16 * 1024 * 4);
+ break;
+ case IB_MAIN:
+ buffer_size = MAX2(buffer_size, 8 * 1024 * 4);
+ break;
+ default:
+ unreachable("unhandled IB type");
+ }
+
+ pb = ws->base.buffer_create(&ws->base, buffer_size,
+ ws->info.gart_page_size,
+ RADEON_DOMAIN_GTT,
+ RADEON_FLAG_CPU_ACCESS);
+ if (!pb)
+ return false;
+
+ mapped = ws->base.buffer_map(pb, NULL, PIPE_TRANSFER_WRITE);
+ if (!mapped) {
+ pb_reference(&pb, NULL);
+ return false;
+ }
+
+ pb_reference(&ib->big_ib_buffer, pb);
+ pb_reference(&pb, NULL);
+
+ ib->ib_mapped = mapped;
+ ib->used_ib_space = 0;
+
+ return true;
+}
+
+static unsigned amdgpu_ib_max_submit_dwords(enum ib_type ib_type)
+{
+ switch (ib_type) {
+ case IB_MAIN:
+ /* Smaller submits means the GPU gets busy sooner and there is less
+ * waiting for buffers and fences. Proof:
+ * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
+ */
+ return 20 * 1024;
+ case IB_CONST_PREAMBLE:
+ case IB_CONST:
+ /* There isn't really any reason to limit CE IB size beyond the natural
+ * limit implied by the main IB, except perhaps GTT size. Just return
+ * an extremely large value that we never get anywhere close to.
+ */
+ return 16 * 1024 * 1024;
+ default:
+ unreachable("bad ib_type");
+ }
+}
+
+static bool amdgpu_get_new_ib(struct radeon_winsys *ws, struct amdgpu_cs *cs,
+ enum ib_type ib_type)
{
struct amdgpu_winsys *aws = (struct amdgpu_winsys*)ws;
/* Small IBs are better than big IBs, because the GPU goes idle quicker
* and there is less waiting for buffers and fences. Proof:
* http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
*/
- unsigned buffer_size, ib_size;
+ struct amdgpu_ib *ib = NULL;
+ struct amdgpu_cs_ib_info *info = &cs->csc->ib[ib_type];
+ unsigned ib_size = 0;
switch (ib_type) {
case IB_CONST_PREAMBLE:
- buffer_size = 4 * 1024 * 4;
- ib_size = 1024 * 4;
+ ib = &cs->const_preamble_ib;
+ ib_size = 256 * 4;
break;
case IB_CONST:
- buffer_size = 512 * 1024 * 4;
- ib_size = 128 * 1024 * 4;
+ ib = &cs->const_ib;
+ ib_size = 8 * 1024 * 4;
break;
case IB_MAIN:
- buffer_size = 128 * 1024 * 4;
- ib_size = 20 * 1024 * 4;
+ ib = &cs->main;
+ ib_size = 4 * 1024 * 4;
break;
default:
unreachable("unhandled IB type");
}
- ib->base.cdw = 0;
- ib->base.buf = NULL;
+ if (!amdgpu_cs_has_chaining(cs->ring_type)) {
+ ib_size = MAX2(ib_size,
+ 4 * MIN2(util_next_power_of_two(ib->max_ib_size),
+ amdgpu_ib_max_submit_dwords(ib_type)));
+ }
+
+ ib->max_ib_size = ib->max_ib_size - ib->max_ib_size / 32;
+
+ ib->base.prev_dw = 0;
+ ib->base.num_prev = 0;
+ ib->base.current.cdw = 0;
+ ib->base.current.buf = NULL;
/* Allocate a new buffer for IBs if the current buffer is all used. */
if (!ib->big_ib_buffer ||
ib->used_ib_space + ib_size > ib->big_ib_buffer->size) {
-
- pb_reference(&ib->big_ib_buffer, NULL);
- ib->ib_mapped = NULL;
- ib->used_ib_space = 0;
-
- ib->big_ib_buffer = ws->buffer_create(ws, buffer_size,
- aws->info.gart_page_size,
- RADEON_DOMAIN_GTT,
- RADEON_FLAG_CPU_ACCESS);
- if (!ib->big_ib_buffer)
+ if (!amdgpu_ib_new_buffer(aws, ib))
return false;
-
- ib->ib_mapped = ws->buffer_map(ib->big_ib_buffer, NULL,
- PIPE_TRANSFER_WRITE);
- if (!ib->ib_mapped) {
- pb_reference(&ib->big_ib_buffer, NULL);
- return false;
- }
}
info->ib_mc_address = amdgpu_winsys_bo(ib->big_ib_buffer)->va +
ib->used_ib_space;
- ib->base.buf = (uint32_t*)(ib->ib_mapped + ib->used_ib_space);
- ib->base.max_dw = ib_size / 4;
+ info->size = 0;
+ ib->ptr_ib_size = &info->size;
+
+ amdgpu_cs_add_buffer(&cs->main.base, ib->big_ib_buffer,
+ RADEON_USAGE_READ, 0, RADEON_PRIO_IB1);
+
+ ib->base.current.buf = (uint32_t*)(ib->ib_mapped + ib->used_ib_space);
+
+ ib_size = ib->big_ib_buffer->size - ib->used_ib_space;
+ ib->base.current.max_dw = ib_size / 4 - amdgpu_cs_epilog_dws(cs->ring_type);
return true;
}
+static void amdgpu_ib_finalize(struct amdgpu_ib *ib)
+{
+ *ib->ptr_ib_size |= ib->base.current.cdw;
+ ib->used_ib_space += ib->base.current.cdw * 4;
+ ib->max_ib_size = MAX2(ib->max_ib_size, ib->base.prev_dw + ib->base.current.cdw);
+}
+
static boolean amdgpu_init_cs_context(struct amdgpu_cs_context *cs,
enum ring_type ring_type)
{
cs->flush_data = flush_ctx;
cs->ring_type = ring_type;
+ cs->main.ib_type = IB_MAIN;
+ cs->const_ib.ib_type = IB_CONST;
+ cs->const_preamble_ib.ib_type = IB_CONST_PREAMBLE;
+
if (!amdgpu_init_cs_context(&cs->csc1, ring_type)) {
FREE(cs);
return NULL;
cs->csc = &cs->csc1;
cs->cst = &cs->csc2;
- if (!amdgpu_get_new_ib(&ctx->ws->base, &cs->main, &cs->csc->ib[IB_MAIN],
- IB_MAIN)) {
+ if (!amdgpu_get_new_ib(&ctx->ws->base, cs, IB_MAIN)) {
amdgpu_destroy_cs_context(&cs->csc2);
amdgpu_destroy_cs_context(&cs->csc1);
FREE(cs);
if (cs->ring_type != RING_GFX || cs->const_ib.ib_mapped)
return NULL;
- if (!amdgpu_get_new_ib(&ws->base, &cs->const_ib, &cs->csc->ib[IB_CONST],
- IB_CONST))
+ if (!amdgpu_get_new_ib(&ws->base, cs, IB_CONST))
return NULL;
cs->csc->request.number_of_ibs = 2;
cs->const_preamble_ib.ib_mapped)
return NULL;
- if (!amdgpu_get_new_ib(&ws->base, &cs->const_preamble_ib,
- &cs->csc->ib[IB_CONST_PREAMBLE], IB_CONST_PREAMBLE))
+ if (!amdgpu_get_new_ib(&ws->base, cs, IB_CONST_PREAMBLE))
return NULL;
cs->csc->request.number_of_ibs = 3;
return &cs->const_preamble_ib.base;
}
-#define OUT_CS(cs, value) (cs)->buf[(cs)->cdw++] = (value)
+#define OUT_CS(cs, value) (cs)->current.buf[(cs)->current.cdw++] = (value)
-int amdgpu_lookup_buffer(struct amdgpu_cs_context *cs, struct amdgpu_winsys_bo *bo)
+static int amdgpu_cs_lookup_buffer(struct radeon_winsys_cs *rcs,
+ struct pb_buffer *buf)
{
- unsigned hash = bo->unique_id & (ARRAY_SIZE(cs->buffer_indices_hashlist)-1);
- int i = cs->buffer_indices_hashlist[hash];
+ struct amdgpu_cs *cs = amdgpu_cs(rcs);
- /* not found or found */
- if (i == -1 || cs->buffers[i].bo == bo)
- return i;
+ return amdgpu_lookup_buffer(cs->csc, (struct amdgpu_winsys_bo*)buf);
+}
- /* Hash collision, look for the BO in the list of buffers linearly. */
- for (i = cs->num_buffers - 1; i >= 0; i--) {
- if (cs->buffers[i].bo == bo) {
- /* Put this buffer in the hash list.
- * This will prevent additional hash collisions if there are
- * several consecutive lookup_buffer calls for the same buffer.
- *
- * Example: Assuming buffers A,B,C collide in the hash list,
- * the following sequence of buffers:
- * AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
- * will collide here: ^ and here: ^,
- * meaning that we should get very few collisions in the end. */
- cs->buffer_indices_hashlist[hash] = i;
- return i;
- }
- }
- return -1;
+static boolean amdgpu_cs_validate(struct radeon_winsys_cs *rcs)
+{
+ return TRUE;
}
-static unsigned amdgpu_add_buffer(struct amdgpu_cs *acs,
- struct amdgpu_winsys_bo *bo,
- enum radeon_bo_usage usage,
- enum radeon_bo_domain domains,
- unsigned priority,
- enum radeon_bo_domain *added_domains)
+static bool amdgpu_cs_check_space(struct radeon_winsys_cs *rcs, unsigned dw)
{
- struct amdgpu_cs_context *cs = acs->csc;
- struct amdgpu_cs_buffer *buffer;
- unsigned hash = bo->unique_id & (ARRAY_SIZE(cs->buffer_indices_hashlist)-1);
- int i = -1;
+ struct amdgpu_ib *ib = amdgpu_ib(rcs);
+ struct amdgpu_cs *cs = amdgpu_cs_from_ib(ib);
+ unsigned requested_size = rcs->prev_dw + rcs->current.cdw + dw;
+ uint64_t va;
+ uint32_t *new_ptr_ib_size;
- assert(priority < 64);
- *added_domains = 0;
+ assert(rcs->current.cdw <= rcs->current.max_dw);
- i = amdgpu_lookup_buffer(cs, bo);
+ if (requested_size > amdgpu_ib_max_submit_dwords(ib->ib_type))
+ return false;
- if (i >= 0) {
- buffer = &cs->buffers[i];
- buffer->priority_usage |= 1llu << priority;
- buffer->usage |= usage;
- *added_domains = domains & ~buffer->domains;
- buffer->domains |= domains;
- cs->flags[i] = MAX2(cs->flags[i], priority / 4);
- return i;
- }
+ ib->max_ib_size = MAX2(ib->max_ib_size, requested_size);
- /* New buffer, check if the backing array is large enough. */
- if (cs->num_buffers >= cs->max_num_buffers) {
- uint32_t size;
- cs->max_num_buffers += 10;
+ if (rcs->current.max_dw - rcs->current.cdw >= dw)
+ return true;
- size = cs->max_num_buffers * sizeof(struct amdgpu_cs_buffer);
- cs->buffers = realloc(cs->buffers, size);
+ if (!amdgpu_cs_has_chaining(cs->ring_type))
+ return false;
- size = cs->max_num_buffers * sizeof(amdgpu_bo_handle);
- cs->handles = realloc(cs->handles, size);
+ /* Allocate a new chunk */
+ if (rcs->num_prev >= rcs->max_prev) {
+ unsigned new_max_prev = MAX2(1, 2 * rcs->max_prev);
+ struct radeon_winsys_cs_chunk *new_prev;
- cs->flags = realloc(cs->flags, cs->max_num_buffers);
+ new_prev = REALLOC(rcs->prev,
+ sizeof(*new_prev) * rcs->max_prev,
+ sizeof(*new_prev) * new_max_prev);
+ if (!new_prev)
+ return false;
+
+ rcs->prev = new_prev;
+ rcs->max_prev = new_max_prev;
}
- /* Initialize the new buffer. */
- cs->buffers[cs->num_buffers].bo = NULL;
- amdgpu_winsys_bo_reference(&cs->buffers[cs->num_buffers].bo, bo);
- cs->handles[cs->num_buffers] = bo->bo;
- cs->flags[cs->num_buffers] = priority / 4;
- p_atomic_inc(&bo->num_cs_references);
- buffer = &cs->buffers[cs->num_buffers];
- buffer->bo = bo;
- buffer->priority_usage = 1llu << priority;
- buffer->usage = usage;
- buffer->domains = domains;
+ if (!amdgpu_ib_new_buffer(cs->ctx->ws, ib))
+ return false;
- cs->buffer_indices_hashlist[hash] = cs->num_buffers;
+ assert(ib->used_ib_space == 0);
+ va = amdgpu_winsys_bo(ib->big_ib_buffer)->va;
- *added_domains = domains;
- return cs->num_buffers++;
-}
+ /* This space was originally reserved. */
+ rcs->current.max_dw += 4;
+ assert(ib->used_ib_space + 4 * rcs->current.max_dw <= ib->big_ib_buffer->size);
-static unsigned amdgpu_cs_add_buffer(struct radeon_winsys_cs *rcs,
- struct pb_buffer *buf,
- enum radeon_bo_usage usage,
- enum radeon_bo_domain domains,
- enum radeon_bo_priority priority)
-{
- /* Don't use the "domains" parameter. Amdgpu doesn't support changing
- * the buffer placement during command submission.
- */
- struct amdgpu_cs *cs = amdgpu_cs(rcs);
- struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)buf;
- enum radeon_bo_domain added_domains;
- unsigned index = amdgpu_add_buffer(cs, bo, usage, bo->initial_domain,
- priority, &added_domains);
+ /* Pad with NOPs and add INDIRECT_BUFFER packet */
+ while ((rcs->current.cdw & 7) != 4)
+ OUT_CS(rcs, 0xffff1000); /* type3 nop packet */
- if (added_domains & RADEON_DOMAIN_VRAM)
- cs->csc->used_vram += bo->base.size;
- else if (added_domains & RADEON_DOMAIN_GTT)
- cs->csc->used_gart += bo->base.size;
+ OUT_CS(rcs, PKT3(ib->ib_type == IB_MAIN ? PKT3_INDIRECT_BUFFER_CIK
+ : PKT3_INDIRECT_BUFFER_CONST, 2, 0));
+ OUT_CS(rcs, va);
+ OUT_CS(rcs, va >> 32);
+ new_ptr_ib_size = &rcs->current.buf[rcs->current.cdw];
+ OUT_CS(rcs, S_3F2_CHAIN(1) | S_3F2_VALID(1));
- return index;
-}
+ assert((rcs->current.cdw & 7) == 0);
+ assert(rcs->current.cdw <= rcs->current.max_dw);
-static int amdgpu_cs_lookup_buffer(struct radeon_winsys_cs *rcs,
- struct pb_buffer *buf)
-{
- struct amdgpu_cs *cs = amdgpu_cs(rcs);
+ *ib->ptr_ib_size |= rcs->current.cdw;
+ ib->ptr_ib_size = new_ptr_ib_size;
- return amdgpu_lookup_buffer(cs->csc, (struct amdgpu_winsys_bo*)buf);
-}
+ /* Hook up the new chunk */
+ rcs->prev[rcs->num_prev].buf = rcs->current.buf;
+ rcs->prev[rcs->num_prev].cdw = rcs->current.cdw;
+ rcs->prev[rcs->num_prev].max_dw = rcs->current.cdw; /* no modifications */
+ rcs->num_prev++;
-static boolean amdgpu_cs_validate(struct radeon_winsys_cs *rcs)
-{
- return TRUE;
+ ib->base.prev_dw += ib->base.current.cdw;
+ ib->base.current.cdw = 0;
+
+ ib->base.current.buf = (uint32_t*)(ib->ib_mapped + ib->used_ib_space);
+ ib->base.current.max_dw = ib->big_ib_buffer->size / 4 - amdgpu_cs_epilog_dws(cs->ring_type);
+
+ amdgpu_cs_add_buffer(&cs->main.base, ib->big_ib_buffer,
+ RADEON_USAGE_READ, 0, RADEON_PRIO_IB1);
+
+ return true;
}
static boolean amdgpu_cs_memory_below_limit(struct radeon_winsys_cs *rcs, uint64_t vram, uint64_t gtt)
int i, r;
cs->request.fence_info.handle = NULL;
- if (cs->request.ip_type != AMDGPU_HW_IP_UVD &&
- cs->request.ip_type != AMDGPU_HW_IP_VCE) {
+ if (amdgpu_cs_has_user_fence(cs)) {
cs->request.fence_info.handle = acs->ctx->user_fence_bo;
cs->request.fence_info.offset = acs->ring_type;
}
} else {
/* Success. */
uint64_t *user_fence = NULL;
- if (cs->request.ip_type != AMDGPU_HW_IP_UVD &&
- cs->request.ip_type != AMDGPU_HW_IP_VCE)
+ if (amdgpu_cs_has_user_fence(cs))
user_fence = acs->ctx->user_fence_cpu_address_base +
cs->request.fence_info.offset;
amdgpu_fence_submitted(cs->fence, &cs->request, user_fence);
struct amdgpu_cs *cs = amdgpu_cs(rcs);
struct amdgpu_winsys *ws = cs->ctx->ws;
+ rcs->current.max_dw += amdgpu_cs_epilog_dws(cs->ring_type);
+
switch (cs->ring_type) {
case RING_DMA:
/* pad DMA ring to 8 DWs */
- while (rcs->cdw & 7)
+ while (rcs->current.cdw & 7)
OUT_CS(rcs, 0x00000000); /* NOP packet */
break;
case RING_GFX:
/* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
- while (rcs->cdw & 7)
+ while (rcs->current.cdw & 7)
OUT_CS(rcs, 0xffff1000); /* type3 nop packet */
/* Also pad the const IB. */
if (cs->const_ib.ib_mapped)
- while (!cs->const_ib.base.cdw || (cs->const_ib.base.cdw & 7))
+ while (!cs->const_ib.base.current.cdw || (cs->const_ib.base.current.cdw & 7))
OUT_CS(&cs->const_ib.base, 0xffff1000); /* type3 nop packet */
if (cs->const_preamble_ib.ib_mapped)
- while (!cs->const_preamble_ib.base.cdw || (cs->const_preamble_ib.base.cdw & 7))
+ while (!cs->const_preamble_ib.base.current.cdw || (cs->const_preamble_ib.base.current.cdw & 7))
OUT_CS(&cs->const_preamble_ib.base, 0xffff1000);
break;
case RING_UVD:
- while (rcs->cdw & 15)
+ while (rcs->current.cdw & 15)
OUT_CS(rcs, 0x80000000); /* type2 nop packet */
break;
default:
break;
}
- if (rcs->cdw > rcs->max_dw) {
+ if (rcs->current.cdw > rcs->current.max_dw) {
fprintf(stderr, "amdgpu: command stream overflowed\n");
}
- amdgpu_cs_add_buffer(rcs, cs->main.big_ib_buffer,
- RADEON_USAGE_READ, 0, RADEON_PRIO_IB1);
-
- if (cs->const_ib.ib_mapped)
- amdgpu_cs_add_buffer(rcs, cs->const_ib.big_ib_buffer,
- RADEON_USAGE_READ, 0, RADEON_PRIO_IB1);
-
- if (cs->const_preamble_ib.ib_mapped)
- amdgpu_cs_add_buffer(rcs, cs->const_preamble_ib.big_ib_buffer,
- RADEON_USAGE_READ, 0, RADEON_PRIO_IB1);
-
/* If the CS is not empty or overflowed.... */
- if (cs->main.base.cdw && cs->main.base.cdw <= cs->main.base.max_dw &&
+ if (radeon_emitted(&cs->main.base, 0) &&
+ cs->main.base.current.cdw <= cs->main.base.current.max_dw &&
!debug_get_option_noop()) {
struct amdgpu_cs_context *cur = cs->csc;
unsigned i, num_buffers = cur->num_buffers;
/* Set IB sizes. */
- cur->ib[IB_MAIN].size = cs->main.base.cdw;
- cs->main.used_ib_space += cs->main.base.cdw * 4;
+ amdgpu_ib_finalize(&cs->main);
- if (cs->const_ib.ib_mapped) {
- cur->ib[IB_CONST].size = cs->const_ib.base.cdw;
- cs->const_ib.used_ib_space += cs->const_ib.base.cdw * 4;
- }
+ if (cs->const_ib.ib_mapped)
+ amdgpu_ib_finalize(&cs->const_ib);
- if (cs->const_preamble_ib.ib_mapped) {
- cur->ib[IB_CONST_PREAMBLE].size = cs->const_preamble_ib.base.cdw;
- cs->const_preamble_ib.used_ib_space += cs->const_preamble_ib.base.cdw * 4;
- }
+ if (cs->const_preamble_ib.ib_mapped)
+ amdgpu_ib_finalize(&cs->const_preamble_ib);
/* Create a fence. */
amdgpu_fence_reference(&cur->fence, NULL);
amdgpu_cs_context_cleanup(cs->csc);
}
- amdgpu_get_new_ib(&ws->base, &cs->main, &cs->csc->ib[IB_MAIN], IB_MAIN);
+ amdgpu_get_new_ib(&ws->base, cs, IB_MAIN);
if (cs->const_ib.ib_mapped)
- amdgpu_get_new_ib(&ws->base, &cs->const_ib, &cs->csc->ib[IB_CONST],
- IB_CONST);
+ amdgpu_get_new_ib(&ws->base, cs, IB_CONST);
if (cs->const_preamble_ib.ib_mapped)
- amdgpu_get_new_ib(&ws->base, &cs->const_preamble_ib,
- &cs->csc->ib[IB_CONST_PREAMBLE], IB_CONST_PREAMBLE);
+ amdgpu_get_new_ib(&ws->base, cs, IB_CONST_PREAMBLE);
ws->num_cs_flushes++;
}
pipe_semaphore_destroy(&cs->flush_completed);
p_atomic_dec(&cs->ctx->ws->num_cs);
pb_reference(&cs->main.big_ib_buffer, NULL);
+ FREE(cs->main.base.prev);
pb_reference(&cs->const_ib.big_ib_buffer, NULL);
+ FREE(cs->const_ib.base.prev);
pb_reference(&cs->const_preamble_ib.big_ib_buffer, NULL);
+ FREE(cs->const_preamble_ib.base.prev);
amdgpu_destroy_cs_context(&cs->csc1);
amdgpu_destroy_cs_context(&cs->csc2);
FREE(cs);
ws->base.cs_add_buffer = amdgpu_cs_add_buffer;
ws->base.cs_lookup_buffer = amdgpu_cs_lookup_buffer;
ws->base.cs_validate = amdgpu_cs_validate;
+ ws->base.cs_check_space = amdgpu_cs_check_space;
ws->base.cs_memory_below_limit = amdgpu_cs_memory_below_limit;
ws->base.cs_query_memory_usage = amdgpu_cs_query_memory_usage;
ws->base.cs_get_buffer_list = amdgpu_cs_get_buffer_list;
projects / mesa.git / blobdiff