winsys/amdgpu: Use amdgpu_winsys helper instead of open-coded casts
[mesa.git] / src / gallium / winsys / amdgpu / drm / amdgpu_surface.c
index cd403f5bfb03e53e3ee4c4094679ac33fb9baafb..aba365f0f49c588af0e3e3a637d64df053d5807e 100644 (file)
  * of the Software.
  */
 
-/* Contact:
- *     Marek Olšák <maraeo@gmail.com>
- */
-
 #include "amdgpu_winsys.h"
 #include "util/u_format.h"
 
@@ -70,7 +66,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
                                enum radeon_surf_mode mode,
                                struct radeon_surf *surf)
 {
-   struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
+   struct amdgpu_winsys *ws = amdgpu_winsys(rws);
    int r;
 
    r = amdgpu_surface_sanity(tex);
@@ -89,15 +85,23 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
    config.info.depth = tex->depth0;
    config.info.array_size = tex->array_size;
    config.info.samples = tex->nr_samples;
+   config.info.storage_samples = tex->nr_storage_samples;
    config.info.levels = tex->last_level + 1;
+   config.info.num_channels = util_format_get_nr_components(tex->format);
    config.is_3d = !!(tex->target == PIPE_TEXTURE_3D);
    config.is_cube = !!(tex->target == PIPE_TEXTURE_CUBE);
-   config.chip_class = ws->info.chip_class;
-   config.num_tile_pipes = ws->info.num_tile_pipes;
-   config.pipe_interleave_bytes = ws->info.pipe_interleave_bytes;
-   config.amdinfo = &ws->amdinfo;
 
-   return ac_compute_surface(ws->addrlib, &config, mode, surf);
+   /* Use different surface counters for color and FMASK, so that MSAA MRTs
+    * always use consecutive surface indices when FMASK is allocated between
+    * them.
+    */
+   config.info.surf_index = &ws->surf_index_color;
+   config.info.fmask_surf_index = &ws->surf_index_fmask;
+
+   if (flags & RADEON_SURF_Z_OR_SBUFFER)
+      config.info.surf_index = NULL;
+
+   return ac_compute_surface(ws->addrlib, &ws->info, &config, mode, surf);
 }
 
 void amdgpu_surface_init_functions(struct amdgpu_winsys *ws)