#include <xf86drm.h>
#include <stdio.h>
#include <sys/stat.h>
-#include "amdgpu_id.h"
+#include "amd/common/amdgpu_id.h"
#define CIK_TILE_MODE_COLOR_2D 14
#define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16 16
#define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16 17
+#ifndef AMDGPU_INFO_NUM_EVICTIONS
+#define AMDGPU_INFO_NUM_EVICTIONS 0x18
+#endif
+
static struct util_hash_table *dev_tab = NULL;
pipe_static_mutex(dev_tab_mutex);
switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d)) {
case CIK__PIPE_CONFIG__ADDR_SURF_P2:
- default:
return 2;
case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16:
case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16:
case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16:
case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16:
return 16;
+ default:
+ fprintf(stderr, "Invalid CIK pipe configuration, assuming P2\n");
+ assert(!"this should never occur");
+ return 2;
}
}
-/* Convert Sea Islands register values GB_ADDR_CFG and MC_ADDR_CFG
- * into GB_TILING_CONFIG register which is only present on R600-R700. */
-static unsigned r600_get_gb_tiling_config(struct amdgpu_gpu_info *info)
-{
- unsigned num_pipes = info->gb_addr_cfg & 0x7;
- unsigned num_banks = info->mc_arb_ramcfg & 0x3;
- unsigned pipe_interleave_bytes = (info->gb_addr_cfg >> 4) & 0x7;
- unsigned row_size = (info->gb_addr_cfg >> 28) & 0x3;
-
- return num_pipes | (num_banks << 4) |
- (pipe_interleave_bytes << 8) |
- (row_size << 12);
-}
-
/* Helper function to do the ioctls needed for setup and init. */
-static boolean do_winsys_init(struct amdgpu_winsys *ws)
+static bool do_winsys_init(struct amdgpu_winsys *ws, int fd)
{
struct amdgpu_buffer_size_alignments alignment_info = {};
- struct amdgpu_heap_info vram, gtt;
+ struct amdgpu_heap_info vram, vram_vis, gtt;
struct drm_amdgpu_info_hw_ip dma = {}, uvd = {}, vce = {};
- uint32_t vce_version = 0, vce_feature = 0;
- int r;
+ uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
+ uint32_t unused_feature;
+ int r, i, j;
+ drmDevicePtr devinfo;
+
+ /* Get PCI info. */
+ r = drmGetDevice(fd, &devinfo);
+ if (r) {
+ fprintf(stderr, "amdgpu: drmGetDevice failed.\n");
+ goto fail;
+ }
+ ws->info.pci_domain = devinfo->businfo.pci->domain;
+ ws->info.pci_bus = devinfo->businfo.pci->bus;
+ ws->info.pci_dev = devinfo->businfo.pci->dev;
+ ws->info.pci_func = devinfo->businfo.pci->func;
+ drmFreeDevice(&devinfo);
/* Query hardware and driver information. */
r = amdgpu_query_gpu_info(ws->dev, &ws->amdinfo);
goto fail;
}
+ r = amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM,
+ AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
+ &vram_vis);
+ if (r) {
+ fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram_vis) failed.\n");
+ goto fail;
+ }
+
r = amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, >t);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
goto fail;
}
+ r = amdgpu_query_firmware_version(ws->dev, AMDGPU_INFO_FW_GFX_ME, 0, 0,
+ &ws->info.me_fw_version, &unused_feature);
+ if (r) {
+ fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(me) failed.\n");
+ goto fail;
+ }
+
+ r = amdgpu_query_firmware_version(ws->dev, AMDGPU_INFO_FW_GFX_PFP, 0, 0,
+ &ws->info.pfp_fw_version, &unused_feature);
+ if (r) {
+ fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(pfp) failed.\n");
+ goto fail;
+ }
+
+ r = amdgpu_query_firmware_version(ws->dev, AMDGPU_INFO_FW_GFX_CE, 0, 0,
+ &ws->info.ce_fw_version, &unused_feature);
+ if (r) {
+ fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(ce) failed.\n");
+ goto fail;
+ }
+
+ r = amdgpu_query_firmware_version(ws->dev, AMDGPU_INFO_FW_UVD, 0, 0,
+ &uvd_version, &uvd_feature);
+ if (r) {
+ fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(uvd) failed.\n");
+ goto fail;
+ }
+
r = amdgpu_query_hw_ip_info(ws->dev, AMDGPU_HW_IP_VCE, 0, &vce);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vce) failed.\n");
ws->info.chip_class = VI;
else if (ws->info.family >= CHIP_BONAIRE)
ws->info.chip_class = CIK;
+ else if (ws->info.family >= CHIP_TAHITI)
+ ws->info.chip_class = SI;
else {
fprintf(stderr, "amdgpu: Unknown family.\n");
goto fail;
}
- /* LLVM 3.6 is required for VI. */
- if (ws->info.chip_class >= VI &&
- (HAVE_LLVM < 0x0306 ||
- (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 1))) {
- fprintf(stderr, "amdgpu: LLVM 3.6.1 is required, got LLVM %i.%i.%i\n",
- HAVE_LLVM >> 8, HAVE_LLVM & 255, MESA_LLVM_VERSION_PATCH);
- goto fail;
- }
-
/* family and rev_id are for addrlib */
switch (ws->info.family) {
+ case CHIP_TAHITI:
+ ws->family = FAMILY_SI;
+ ws->rev_id = SI_TAHITI_P_A0;
+ break;
+ case CHIP_PITCAIRN:
+ ws->family = FAMILY_SI;
+ ws->rev_id = SI_PITCAIRN_PM_A0;
+ break;
+ case CHIP_VERDE:
+ ws->family = FAMILY_SI;
+ ws->rev_id = SI_CAPEVERDE_M_A0;
+ break;
+ case CHIP_OLAND:
+ ws->family = FAMILY_SI;
+ ws->rev_id = SI_OLAND_M_A0;
+ break;
+ case CHIP_HAINAN:
+ ws->family = FAMILY_SI;
+ ws->rev_id = SI_HAINAN_V_A0;
+ break;
case CHIP_BONAIRE:
ws->family = FAMILY_CI;
ws->rev_id = CI_BONAIRE_M_A0;
break;
case CHIP_CARRIZO:
ws->family = FAMILY_CZ;
- ws->rev_id = CZ_CARRIZO_A0;
+ ws->rev_id = CARRIZO_A0;
+ break;
+ case CHIP_STONEY:
+ ws->family = FAMILY_CZ;
+ ws->rev_id = STONEY_A0;
break;
case CHIP_FIJI:
ws->family = FAMILY_VI;
ws->rev_id = VI_FIJI_P_A0;
break;
+ case CHIP_POLARIS10:
+ ws->family = FAMILY_VI;
+ ws->rev_id = VI_POLARIS10_P_A0;
+ break;
+ case CHIP_POLARIS11:
+ ws->family = FAMILY_VI;
+ ws->rev_id = VI_POLARIS11_M_A0;
+ break;
+ case CHIP_POLARIS12:
+ ws->family = FAMILY_VI;
+ ws->rev_id = VI_POLARIS12_V_A0;
+ break;
default:
fprintf(stderr, "amdgpu: Unknown family.\n");
goto fail;
goto fail;
}
+ /* Set which chips have dedicated VRAM. */
+ ws->info.has_dedicated_vram =
+ !(ws->amdinfo.ids_flags & AMDGPU_IDS_FLAGS_FUSION);
+
/* Set hardware information. */
ws->info.gart_size = gtt.heap_size;
ws->info.vram_size = vram.heap_size;
+ ws->info.vram_vis_size = vram_vis.heap_size;
+ /* The kernel can split large buffers in VRAM but not in GTT, so large
+ * allocations can fail or cause buffer movement failures in the kernel.
+ */
+ ws->info.max_alloc_size = MIN2(ws->info.vram_size * 0.9, ws->info.gart_size * 0.7);
/* convert the shader clock from KHz to MHz */
- ws->info.max_sclk = ws->amdinfo.max_engine_clk / 1000;
- ws->info.max_compute_units = 1; /* TODO */
+ ws->info.max_shader_clock = ws->amdinfo.max_engine_clk / 1000;
ws->info.max_se = ws->amdinfo.num_shader_engines;
ws->info.max_sh_per_se = ws->amdinfo.num_shader_arrays_per_engine;
ws->info.has_uvd = uvd.available_rings != 0;
+ ws->info.uvd_fw_version =
+ uvd.available_rings ? uvd_version : 0;
ws->info.vce_fw_version =
vce.available_rings ? vce_version : 0;
- ws->info.has_userptr = TRUE;
- ws->info.r600_num_backends = ws->amdinfo.rb_pipes;
- ws->info.r600_clock_crystal_freq = ws->amdinfo.gpu_counter_freq;
- ws->info.r600_tiling_config = r600_get_gb_tiling_config(&ws->amdinfo);
- ws->info.r600_num_tile_pipes = cik_get_num_tile_pipes(&ws->amdinfo);
- ws->info.r600_max_pipes = ws->amdinfo.max_quad_shader_pipes; /* TODO: is this correct? */
- ws->info.r600_virtual_address = TRUE;
- ws->info.r600_has_dma = dma.available_rings != 0;
+ ws->info.has_userptr = true;
+ ws->info.num_render_backends = ws->amdinfo.rb_pipes;
+ ws->info.clock_crystal_freq = ws->amdinfo.gpu_counter_freq;
+ ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */
+ ws->info.num_tile_pipes = cik_get_num_tile_pipes(&ws->amdinfo);
+ ws->info.pipe_interleave_bytes = 256 << ((ws->amdinfo.gb_addr_cfg >> 4) & 0x7);
+ ws->info.has_virtual_memory = true;
+ ws->info.has_sdma = dma.available_rings != 0;
+
+ /* Get the number of good compute units. */
+ ws->info.num_good_compute_units = 0;
+ for (i = 0; i < ws->info.max_se; i++)
+ for (j = 0; j < ws->info.max_sh_per_se; j++)
+ ws->info.num_good_compute_units +=
+ util_bitcount(ws->amdinfo.cu_bitmap[i][j]);
memcpy(ws->info.si_tile_mode_array, ws->amdinfo.gb_tile_mode,
sizeof(ws->amdinfo.gb_tile_mode));
- ws->info.si_tile_mode_array_valid = TRUE;
- ws->info.si_backend_enabled_mask = ws->amdinfo.enabled_rb_pipes_mask;
+ ws->info.enabled_rb_mask = ws->amdinfo.enabled_rb_pipes_mask;
memcpy(ws->info.cik_macrotile_mode_array, ws->amdinfo.gb_macro_tile_mode,
sizeof(ws->amdinfo.gb_macro_tile_mode));
- ws->info.cik_macrotile_mode_array_valid = TRUE;
- ws->gart_page_size = alignment_info.size_remote;
+ ws->info.gart_page_size = alignment_info.size_remote;
+
+ if (ws->info.chip_class == SI)
+ ws->info.gfx_ib_pad_with_type2 = TRUE;
- return TRUE;
+ ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;
+
+ return true;
fail:
if (ws->addrlib)
AddrDestroy(ws->addrlib);
amdgpu_device_deinitialize(ws->dev);
ws->dev = NULL;
- return FALSE;
+ return false;
+}
+
+static void do_winsys_deinit(struct amdgpu_winsys *ws)
+{
+ AddrDestroy(ws->addrlib);
+ amdgpu_device_deinitialize(ws->dev);
}
static void amdgpu_winsys_destroy(struct radeon_winsys *rws)
{
struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
- pipe_mutex_destroy(ws->bo_fence_lock);
+ if (util_queue_is_initialized(&ws->cs_queue))
+ util_queue_destroy(&ws->cs_queue);
- ws->cman->destroy(ws->cman);
- ws->kman->destroy(ws->kman);
- AddrDestroy(ws->addrlib);
-
- amdgpu_device_deinitialize(ws->dev);
+ pipe_mutex_destroy(ws->bo_fence_lock);
+ pb_slabs_deinit(&ws->bo_slabs);
+ pb_cache_deinit(&ws->bo_cache);
+ pipe_mutex_destroy(ws->global_bo_list_lock);
+ do_winsys_deinit(ws);
FREE(rws);
}
*info = ((struct amdgpu_winsys *)rws)->info;
}
-static boolean amdgpu_cs_request_feature(struct radeon_winsys_cs *rcs,
- enum radeon_feature_id fid,
- boolean enable)
+static bool amdgpu_cs_request_feature(struct radeon_winsys_cs *rcs,
+ enum radeon_feature_id fid,
+ bool enable)
{
- return FALSE;
+ return false;
}
static uint64_t amdgpu_query_value(struct radeon_winsys *rws,
return ws->allocated_vram;
case RADEON_REQUESTED_GTT_MEMORY:
return ws->allocated_gtt;
+ case RADEON_MAPPED_VRAM:
+ return ws->mapped_vram;
+ case RADEON_MAPPED_GTT:
+ return ws->mapped_gtt;
case RADEON_BUFFER_WAIT_TIME_NS:
return ws->buffer_wait_time;
+ case RADEON_NUM_MAPPED_BUFFERS:
+ return ws->num_mapped_buffers;
case RADEON_TIMESTAMP:
amdgpu_query_info(ws->dev, AMDGPU_INFO_TIMESTAMP, 8, &retval);
return retval;
- case RADEON_NUM_CS_FLUSHES:
- return ws->num_cs_flushes;
+ case RADEON_NUM_GFX_IBS:
+ return ws->num_gfx_IBs;
+ case RADEON_NUM_SDMA_IBS:
+ return ws->num_sdma_IBs;
case RADEON_NUM_BYTES_MOVED:
amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_BYTES_MOVED, 8, &retval);
return retval;
+ case RADEON_NUM_EVICTIONS:
+ amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_EVICTIONS, 8, &retval);
+ return retval;
case RADEON_VRAM_USAGE:
amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &heap);
return heap.heap_usage;
+ case RADEON_VRAM_VIS_USAGE:
+ amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM,
+ AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &heap);
+ return heap.heap_usage;
case RADEON_GTT_USAGE:
amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, &heap);
return heap.heap_usage;
case RADEON_GPU_RESET_COUNTER:
assert(0);
return 0;
+ case RADEON_CS_THREAD_TIME:
+ return util_queue_get_thread_time_nano(&ws->cs_queue, 0);
}
return 0;
}
return key1 != key2;
}
-static bool amdgpu_winsys_unref(struct radeon_winsys *ws)
+static bool amdgpu_winsys_unref(struct radeon_winsys *rws)
{
- struct amdgpu_winsys *rws = (struct amdgpu_winsys*)ws;
+ struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
bool destroy;
/* When the reference counter drops to zero, remove the device pointer
* from the table when the counter drops to 0. */
pipe_mutex_lock(dev_tab_mutex);
- destroy = pipe_reference(&rws->reference, NULL);
+ destroy = pipe_reference(&ws->reference, NULL);
if (destroy && dev_tab)
- util_hash_table_remove(dev_tab, rws->dev);
+ util_hash_table_remove(dev_tab, ws->dev);
pipe_mutex_unlock(dev_tab_mutex);
return destroy;
/* Create a new winsys. */
ws = CALLOC_STRUCT(amdgpu_winsys);
- if (!ws) {
- pipe_mutex_unlock(dev_tab_mutex);
- return NULL;
- }
+ if (!ws)
+ goto fail;
ws->dev = dev;
ws->info.drm_major = drm_major;
ws->info.drm_minor = drm_minor;
- if (!do_winsys_init(ws))
- goto fail;
+ if (!do_winsys_init(ws, fd))
+ goto fail_alloc;
/* Create managers. */
- ws->kman = amdgpu_bomgr_create(ws);
- if (!ws->kman)
- goto fail;
- ws->cman = pb_cache_manager_create(ws->kman, 500000, 2.0f, 0,
- (ws->info.vram_size + ws->info.gart_size) / 8);
- if (!ws->cman)
- goto fail;
+ pb_cache_init(&ws->bo_cache, 500000, ws->check_vm ? 1.0f : 2.0f, 0,
+ (ws->info.vram_size + ws->info.gart_size) / 8,
+ amdgpu_bo_destroy, amdgpu_bo_can_reclaim);
+
+ if (!pb_slabs_init(&ws->bo_slabs,
+ AMDGPU_SLAB_MIN_SIZE_LOG2, AMDGPU_SLAB_MAX_SIZE_LOG2,
+ 12, /* number of heaps (domain/flags combinations) */
+ ws,
+ amdgpu_bo_can_reclaim_slab,
+ amdgpu_bo_slab_alloc,
+ amdgpu_bo_slab_free))
+ goto fail_cache;
+
+ ws->info.min_alloc_size = 1 << AMDGPU_SLAB_MIN_SIZE_LOG2;
/* init reference */
pipe_reference_init(&ws->reference, 1);
ws->base.query_value = amdgpu_query_value;
ws->base.read_registers = amdgpu_read_registers;
- amdgpu_bomgr_init_functions(ws);
+ amdgpu_bo_init_functions(ws);
amdgpu_cs_init_functions(ws);
amdgpu_surface_init_functions(ws);
+ LIST_INITHEAD(&ws->global_bo_list);
+ pipe_mutex_init(ws->global_bo_list_lock);
pipe_mutex_init(ws->bo_fence_lock);
+ if (!util_queue_init(&ws->cs_queue, "amdgpu_cs", 8, 1)) {
+ amdgpu_winsys_destroy(&ws->base);
+ pipe_mutex_unlock(dev_tab_mutex);
+ return NULL;
+ }
+
/* Create the screen at the end. The winsys must be initialized
* completely.
*
return &ws->base;
+fail_cache:
+ pb_cache_deinit(&ws->bo_cache);
+ do_winsys_deinit(ws);
+fail_alloc:
+ FREE(ws);
fail:
pipe_mutex_unlock(dev_tab_mutex);
- if (ws->cman)
- ws->cman->destroy(ws->cman);
- if (ws->kman)
- ws->kman->destroy(ws->kman);
- FREE(ws);
return NULL;
}
projects / mesa.git / blobdiff