#include <xf86drm.h>
#include <stdio.h>
#include <sys/stat.h>
+#include "amd/common/ac_llvm_util.h"
#include "amd/common/sid.h"
#include "amd/common/gfx9d.h"
DEBUG_GET_ONCE_BOOL_OPTION(all_bos, "RADEON_ALL_BOS", false)
+static void handle_env_var_force_family(struct amdgpu_winsys *ws)
+{
+ const char *family = debug_get_option("SI_FORCE_FAMILY", NULL);
+ unsigned i;
+
+ if (!family)
+ return;
+
+ for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
+ if (!strcmp(family, ac_get_llvm_processor_name(i))) {
+ /* Override family and chip_class. */
+ ws->info.family = i;
+ ws->info.name = "GCN-NOOP";
+
+ if (i >= CHIP_VEGA10)
+ ws->info.chip_class = GFX9;
+ else if (i >= CHIP_TONGA)
+ ws->info.chip_class = VI;
+ else if (i >= CHIP_BONAIRE)
+ ws->info.chip_class = CIK;
+ else
+ ws->info.chip_class = SI;
+
+ /* Don't submit any IBs. */
+ setenv("RADEON_NOOP", "1", 1);
+ return;
+ }
+ }
+
+ fprintf(stderr, "radeonsi: Unknown family: %s\n", family);
+ exit(1);
+}
+
/* Helper function to do the ioctls needed for setup and init. */
static bool do_winsys_init(struct amdgpu_winsys *ws,
const struct pipe_screen_config *config,
if (!ac_query_gpu_info(fd, ws->dev, &ws->info, &ws->amdinfo))
goto fail;
+ handle_env_var_force_family(ws);
+
ws->addrlib = amdgpu_addr_create(&ws->info, &ws->amdinfo, &ws->info.max_alignment);
if (!ws->addrlib) {
fprintf(stderr, "amdgpu: Cannot create addrlib.\n");
util_queue_destroy(&ws->cs_queue);
simple_mtx_destroy(&ws->bo_fence_lock);
- pb_slabs_deinit(&ws->bo_slabs);
+ for (unsigned i = 0; i < NUM_SLAB_ALLOCATORS; i++) {
+ if (ws->bo_slabs[i].groups)
+ pb_slabs_deinit(&ws->bo_slabs[i]);
+ }
pb_cache_deinit(&ws->bo_cache);
util_hash_table_destroy(ws->bo_export_table);
simple_mtx_destroy(&ws->global_bo_list_lock);
if (ws) {
pipe_reference(NULL, &ws->reference);
simple_mtx_unlock(&dev_tab_mutex);
+
+ /* Release the device handle, because we don't need it anymore.
+ * This function is returning an existing winsys instance, which
+ * has its own device handle.
+ */
+ amdgpu_device_deinitialize(dev);
return &ws->base;
}
(ws->info.vram_size + ws->info.gart_size) / 8,
amdgpu_bo_destroy, amdgpu_bo_can_reclaim);
- if (!pb_slabs_init(&ws->bo_slabs,
- AMDGPU_SLAB_MIN_SIZE_LOG2, AMDGPU_SLAB_MAX_SIZE_LOG2,
- RADEON_MAX_SLAB_HEAPS,
- ws,
- amdgpu_bo_can_reclaim_slab,
- amdgpu_bo_slab_alloc,
- amdgpu_bo_slab_free))
- goto fail_cache;
+ unsigned min_slab_order = 9; /* 512 bytes */
+ unsigned max_slab_order = 18; /* 256 KB - higher numbers increase memory usage */
+ unsigned num_slab_orders_per_allocator = (max_slab_order - min_slab_order) /
+ NUM_SLAB_ALLOCATORS;
+
+ /* Divide the size order range among slab managers. */
+ for (unsigned i = 0; i < NUM_SLAB_ALLOCATORS; i++) {
+ unsigned min_order = min_slab_order;
+ unsigned max_order = MIN2(min_order + num_slab_orders_per_allocator,
+ max_slab_order);
+
+ if (!pb_slabs_init(&ws->bo_slabs[i],
+ min_order, max_order,
+ RADEON_MAX_SLAB_HEAPS,
+ ws,
+ amdgpu_bo_can_reclaim_slab,
+ amdgpu_bo_slab_alloc,
+ amdgpu_bo_slab_free)) {
+ amdgpu_winsys_destroy(&ws->base);
+ simple_mtx_unlock(&dev_tab_mutex);
+ return NULL;
+ }
+
+ min_slab_order = max_order + 1;
+ }
- ws->info.min_alloc_size = 1 << AMDGPU_SLAB_MIN_SIZE_LOG2;
+ ws->info.min_alloc_size = 1 << ws->bo_slabs[0].min_order;
/* init reference */
pipe_reference_init(&ws->reference, 1);