#include "util/u_inlines.h"
#include "util/u_memory.h"
#include "util/u_debug.h"
-#include "../intel_winsys.h"
-
-#define BATCH_SZ (8192 * sizeof(uint32_t))
+#include "intel_drm_public.h"
struct intel_winsys {
int fd;
struct drm_intel_decode *decode;
};
+static drm_intel_context *
+gem_ctx(const struct intel_context *ctx)
+{
+ return (drm_intel_context *) ctx;
+}
+
static drm_intel_bo *
gem_bo(const struct intel_bo *bo)
{
info->devid = drm_intel_bufmgr_gem_get_devid(winsys->bufmgr);
- info->max_batch_size = BATCH_SZ;
+ if (drm_intel_get_aperture_sizes(winsys->fd,
+ &info->aperture_mappable, &info->aperture_total)) {
+ debug_error("failed to query aperture sizes");
+ return false;
+ }
get_param(winsys, I915_PARAM_HAS_LLC, &val);
info->has_llc = val;
struct intel_winsys *
intel_winsys_create_for_fd(int fd)
{
+ /* so that we can have enough (up to 4094) relocs per bo */
+ const int batch_size = sizeof(uint32_t) * 8192;
struct intel_winsys *winsys;
winsys = CALLOC_STRUCT(intel_winsys);
winsys->fd = fd;
- winsys->bufmgr = drm_intel_bufmgr_gem_init(winsys->fd, BATCH_SZ);
+ winsys->bufmgr = drm_intel_bufmgr_gem_init(winsys->fd, batch_size);
if (!winsys->bufmgr) {
debug_error("failed to create GEM buffer manager");
FREE(winsys);
/*
* No need to implicitly set up a fence register for each non-linear reloc
- * entry. When a fence register is needed for a reloc entry,
- * drm_intel_bo_emit_reloc_fence() will be called explicitly.
- *
- * intel_bo_add_reloc() currently lacks "bool fenced" for this to work.
- * But we never need a fence register on GEN4+ so we do not need to worry
- * about it yet.
+ * entry. INTEL_RELOC_FENCE will be set on reloc entries that need them.
*/
drm_intel_bufmgr_gem_enable_fenced_relocs(winsys->bufmgr);
intel_winsys_destroy_context(struct intel_winsys *winsys,
struct intel_context *ctx)
{
- drm_intel_gem_context_destroy((drm_intel_context *) ctx);
+ drm_intel_gem_context_destroy(gem_ctx(ctx));
}
int
return drm_intel_reg_read(winsys->bufmgr, reg, val);
}
+int
+intel_winsys_get_reset_stats(struct intel_winsys *winsys,
+ struct intel_context *ctx,
+ uint32_t *active_lost,
+ uint32_t *pending_lost)
+{
+ uint32_t reset_count;
+
+ return drm_intel_get_reset_stats(gem_ctx(ctx),
+ &reset_count, active_lost, pending_lost);
+}
+
struct intel_bo *
intel_winsys_alloc_bo(struct intel_winsys *winsys,
const char *name,
- enum intel_tiling_mode tiling,
- unsigned long pitch,
- unsigned long height,
- uint32_t initial_domain)
+ unsigned long size,
+ bool cpu_init)
{
- const bool for_render =
- (initial_domain & (INTEL_DOMAIN_RENDER | INTEL_DOMAIN_INSTRUCTION));
const unsigned int alignment = 4096; /* always page-aligned */
- unsigned long size;
drm_intel_bo *bo;
- switch (tiling) {
- case INTEL_TILING_X:
- if (pitch % 512)
- return NULL;
- break;
- case INTEL_TILING_Y:
- if (pitch % 128)
- return NULL;
- break;
- default:
- break;
- }
-
- if (pitch > ULONG_MAX / height)
- return NULL;
-
- size = pitch * height;
-
- if (for_render) {
+ if (cpu_init) {
+ bo = drm_intel_bo_alloc(winsys->bufmgr, name, size, alignment);
+ } else {
bo = drm_intel_bo_alloc_for_render(winsys->bufmgr,
name, size, alignment);
}
- else {
- bo = drm_intel_bo_alloc(winsys->bufmgr, name, size, alignment);
- }
-
- if (bo && tiling != INTEL_TILING_NONE) {
- uint32_t real_tiling = tiling;
- int err;
-
- err = drm_intel_bo_set_tiling(bo, &real_tiling, pitch);
- if (err || real_tiling != tiling) {
- assert(!"tiling mismatch");
- drm_intel_bo_unreference(bo);
- return NULL;
- }
- }
return (struct intel_bo *) bo;
}
+struct intel_bo *
+intel_winsys_import_userptr(struct intel_winsys *winsys,
+ const char *name,
+ void *userptr,
+ unsigned long size,
+ unsigned long flags)
+{
+ return NULL;
+}
+
struct intel_bo *
intel_winsys_import_handle(struct intel_winsys *winsys,
const char *name,
drm_intel_bo *bo;
int err;
+ if (handle->offset != 0) {
+ debug_error("attempt to import unsupported winsys offset");
+ return NULL;
+ }
+
switch (handle->type) {
case DRM_API_HANDLE_TYPE_SHARED:
{
intel_bo_unmap(bo);
}
-void
-intel_bo_reference(struct intel_bo *bo)
+struct intel_bo *
+intel_bo_ref(struct intel_bo *bo)
{
- drm_intel_bo_reference(gem_bo(bo));
+ if (bo)
+ drm_intel_bo_reference(gem_bo(bo));
+
+ return bo;
}
void
-intel_bo_unreference(struct intel_bo *bo)
+intel_bo_unref(struct intel_bo *bo)
{
- drm_intel_bo_unreference(gem_bo(bo));
+ if (bo)
+ drm_intel_bo_unreference(gem_bo(bo));
+}
+
+int
+intel_bo_set_tiling(struct intel_bo *bo,
+ enum intel_tiling_mode tiling,
+ unsigned long pitch)
+{
+ uint32_t real_tiling = tiling;
+ int err;
+
+ switch (tiling) {
+ case INTEL_TILING_X:
+ if (pitch % 512)
+ return -1;
+ break;
+ case INTEL_TILING_Y:
+ if (pitch % 128)
+ return -1;
+ break;
+ default:
+ break;
+ }
+
+ err = drm_intel_bo_set_tiling(gem_bo(bo), &real_tiling, pitch);
+ if (err || real_tiling != tiling) {
+ assert(!"tiling mismatch");
+ return -1;
+ }
+
+ return 0;
}
void *
return gem_bo(bo)->virtual;
}
+void *
+intel_bo_map_async(struct intel_bo *bo)
+{
+ return NULL;
+}
+
void *
intel_bo_map_gtt(struct intel_bo *bo)
{
}
void *
-intel_bo_map_unsynchronized(struct intel_bo *bo)
+intel_bo_map_gtt_async(struct intel_bo *bo)
{
int err;
int
intel_bo_add_reloc(struct intel_bo *bo, uint32_t offset,
struct intel_bo *target_bo, uint32_t target_offset,
- uint32_t read_domains, uint32_t write_domain,
- uint64_t *presumed_offset)
+ uint32_t flags, uint64_t *presumed_offset)
{
+ uint32_t read_domains, write_domain;
int err;
- err = drm_intel_bo_emit_reloc(gem_bo(bo), offset,
- gem_bo(target_bo), target_offset,
- read_domains, write_domain);
+ if (flags & INTEL_RELOC_WRITE) {
+ /*
+ * Because of the translation to domains, INTEL_RELOC_GGTT should only
+ * be set on GEN6 when the bo is written by MI_* or PIPE_CONTROL. The
+ * kernel will translate it back to INTEL_RELOC_GGTT.
+ */
+ write_domain = (flags & INTEL_RELOC_GGTT) ?
+ I915_GEM_DOMAIN_INSTRUCTION : I915_GEM_DOMAIN_RENDER;
+ read_domains = write_domain;
+ } else {
+ write_domain = 0;
+ read_domains = I915_GEM_DOMAIN_RENDER |
+ I915_GEM_DOMAIN_SAMPLER |
+ I915_GEM_DOMAIN_INSTRUCTION |
+ I915_GEM_DOMAIN_VERTEX;
+ }
+
+ if (flags & INTEL_RELOC_FENCE) {
+ err = drm_intel_bo_emit_reloc_fence(gem_bo(bo), offset,
+ gem_bo(target_bo), target_offset,
+ read_domains, write_domain);
+ } else {
+ err = drm_intel_bo_emit_reloc(gem_bo(bo), offset,
+ gem_bo(target_bo), target_offset,
+ read_domains, write_domain);
+ }
*presumed_offset = gem_bo(target_bo)->offset64 + target_offset;
{
int err;
- err = drm_intel_gem_bo_wait(gem_bo(bo), timeout);
+ if (timeout >= 0) {
+ err = drm_intel_gem_bo_wait(gem_bo(bo), timeout);
+ } else {
+ drm_intel_bo_wait_rendering(gem_bo(bo));
+ err = 0;
+ }
+
/* consider the bo idle on errors */
if (err && err != -ETIME)
err = 0;
projects / mesa.git / blobdiff