ilo: EOL unplumb unmaintained gallium drv from winsys

[mesa.git] / src / gallium / winsys / intel / drm / intel_drm_winsys.c

diff --git a/src/gallium/winsys/intel/drm/intel_drm_winsys.c b/src/gallium/winsys/intel/drm/intel_drm_winsys.c
index c8ae6c16a8c297426ea24786f8702fbd30f8c803..63c5c8b0acf46dcf217b11bacfaec6e6c964e392 100644 (file)
--- a/src/gallium/winsys/intel/drm/intel_drm_winsys.c
+++ b/src/gallium/winsys/intel/drm/intel_drm_winsys.c
@@ -41,9 +41,7 @@
 #include "util/u_inlines.h"
 #include "util/u_memory.h"
 #include "util/u_debug.h"
-#include "../intel_winsys.h"
-
-#define BATCH_SZ (8192 * sizeof(uint32_t))
+#include "intel_drm_public.h"
 
 struct intel_winsys {
    int fd;
@@ -56,6 +54,12 @@ struct intel_winsys {
    struct drm_intel_decode *decode;
 };
 
+static drm_intel_context *
+gem_ctx(const struct intel_context *ctx)
+{
+   return (drm_intel_context *) ctx;
+}
+
 static drm_intel_bo *
 gem_bo(const struct intel_bo *bo)
 {
@@ -145,8 +149,6 @@ probe_winsys(struct intel_winsys *winsys)
       return false;
    }
 
-   info->max_batch_size = BATCH_SZ;
-
    get_param(winsys, I915_PARAM_HAS_LLC, &val);
    info->has_llc = val;
    info->has_address_swizzling = test_address_swizzling(winsys);
@@ -169,6 +171,8 @@ probe_winsys(struct intel_winsys *winsys)
 struct intel_winsys *
 intel_winsys_create_for_fd(int fd)
 {
+   /* so that we can have enough (up to 4094) relocs per bo */
+   const int batch_size = sizeof(uint32_t) * 8192;
    struct intel_winsys *winsys;
 
    winsys = CALLOC_STRUCT(intel_winsys);
@@ -177,7 +181,7 @@ intel_winsys_create_for_fd(int fd)
 
    winsys->fd = fd;
 
-   winsys->bufmgr = drm_intel_bufmgr_gem_init(winsys->fd, BATCH_SZ);
+   winsys->bufmgr = drm_intel_bufmgr_gem_init(winsys->fd, batch_size);
    if (!winsys->bufmgr) {
       debug_error("failed to create GEM buffer manager");
       FREE(winsys);
@@ -245,7 +249,7 @@ void
 intel_winsys_destroy_context(struct intel_winsys *winsys,
                              struct intel_context *ctx)
 {
-   drm_intel_gem_context_destroy((drm_intel_context *) ctx);
+   drm_intel_gem_context_destroy(gem_ctx(ctx));
 }
 
 int
@@ -255,59 +259,47 @@ intel_winsys_read_reg(struct intel_winsys *winsys,
    return drm_intel_reg_read(winsys->bufmgr, reg, val);
 }
 
+int
+intel_winsys_get_reset_stats(struct intel_winsys *winsys,
+                             struct intel_context *ctx,
+                             uint32_t *active_lost,
+                             uint32_t *pending_lost)
+{
+   uint32_t reset_count;
+
+   return drm_intel_get_reset_stats(gem_ctx(ctx),
+         &reset_count, active_lost, pending_lost);
+}
+
 struct intel_bo *
 intel_winsys_alloc_bo(struct intel_winsys *winsys,
                       const char *name,
-                      enum intel_tiling_mode tiling,
-                      unsigned long pitch,
-                      unsigned long height,
+                      unsigned long size,
                       bool cpu_init)
 {
    const unsigned int alignment = 4096; /* always page-aligned */
-   unsigned long size;
    drm_intel_bo *bo;
 
-   switch (tiling) {
-   case INTEL_TILING_X:
-      if (pitch % 512)
-         return NULL;
-      break;
-   case INTEL_TILING_Y:
-      if (pitch % 128)
-         return NULL;
-      break;
-   default:
-      break;
-   }
-
-   if (pitch > ULONG_MAX / height)
-      return NULL;
-
-   size = pitch * height;
-
    if (cpu_init) {
       bo = drm_intel_bo_alloc(winsys->bufmgr, name, size, alignment);
-   }
-   else {
+   } else {
       bo = drm_intel_bo_alloc_for_render(winsys->bufmgr,
             name, size, alignment);
    }
 
-   if (bo && tiling != INTEL_TILING_NONE) {
-      uint32_t real_tiling = tiling;
-      int err;
-
-      err = drm_intel_bo_set_tiling(bo, &real_tiling, pitch);
-      if (err || real_tiling != tiling) {
-         assert(!"tiling mismatch");
-         drm_intel_bo_unreference(bo);
-         return NULL;
-      }
-   }
-
    return (struct intel_bo *) bo;
 }
 
+struct intel_bo *
+intel_winsys_import_userptr(struct intel_winsys *winsys,
+                            const char *name,
+                            void *userptr,
+                            unsigned long size,
+                            unsigned long flags)
+{
+   return NULL;
+}
+
 struct intel_bo *
 intel_winsys_import_handle(struct intel_winsys *winsys,
                            const char *name,
@@ -320,6 +312,11 @@ intel_winsys_import_handle(struct intel_winsys *winsys,
    drm_intel_bo *bo;
    int err;
 
+   if (handle->offset != 0) {
+      debug_error("attempt to import unsupported winsys offset");
+      return NULL;
+   }
+
    switch (handle->type) {
    case DRM_API_HANDLE_TYPE_SHARED:
       {
@@ -471,16 +468,50 @@ intel_winsys_decode_bo(struct intel_winsys *winsys,
    intel_bo_unmap(bo);
 }
 
-void
-intel_bo_reference(struct intel_bo *bo)
+struct intel_bo *
+intel_bo_ref(struct intel_bo *bo)
 {
-   drm_intel_bo_reference(gem_bo(bo));
+   if (bo)
+      drm_intel_bo_reference(gem_bo(bo));
+
+   return bo;
 }
 
 void
-intel_bo_unreference(struct intel_bo *bo)
+intel_bo_unref(struct intel_bo *bo)
 {
-   drm_intel_bo_unreference(gem_bo(bo));
+   if (bo)
+      drm_intel_bo_unreference(gem_bo(bo));
+}
+
+int
+intel_bo_set_tiling(struct intel_bo *bo,
+                    enum intel_tiling_mode tiling,
+                    unsigned long pitch)
+{
+   uint32_t real_tiling = tiling;
+   int err;
+
+   switch (tiling) {
+   case INTEL_TILING_X:
+      if (pitch % 512)
+         return -1;
+      break;
+   case INTEL_TILING_Y:
+      if (pitch % 128)
+         return -1;
+      break;
+   default:
+      break;
+   }
+
+   err = drm_intel_bo_set_tiling(gem_bo(bo), &real_tiling, pitch);
+   if (err || real_tiling != tiling) {
+      assert(!"tiling mismatch");
+      return -1;
+   }
+
+   return 0;
 }
 
 void *
@@ -497,6 +528,12 @@ intel_bo_map(struct intel_bo *bo, bool write_enable)
    return gem_bo(bo)->virtual;
 }
 
+void *
+intel_bo_map_async(struct intel_bo *bo)
+{
+   return NULL;
+}
+
 void *
 intel_bo_map_gtt(struct intel_bo *bo)
 {
@@ -512,7 +549,7 @@ intel_bo_map_gtt(struct intel_bo *bo)
 }
 
 void *
-intel_bo_map_unsynchronized(struct intel_bo *bo)
+intel_bo_map_gtt_async(struct intel_bo *bo)
 {
    int err;
 
@@ -611,7 +648,13 @@ intel_bo_wait(struct intel_bo *bo, int64_t timeout)
 {
    int err;
 
-   err = drm_intel_gem_bo_wait(gem_bo(bo), timeout);
+   if (timeout >= 0) {
+      err = drm_intel_gem_bo_wait(gem_bo(bo), timeout);
+   } else {
+      drm_intel_bo_wait_rendering(gem_bo(bo));
+      err = 0;
+   }
+
    /* consider the bo idle on errors */
    if (err && err != -ETIME)
       err = 0;