return -EINVAL;
}
- radeon->tiling_info.num_banks = (tiling_config & 0xf0) >> 4;
+ switch ((tiling_config & 0xf0) >> 4) {
+ case 0:
+ radeon->tiling_info.num_banks = 4;
+ break;
+ case 1:
+ radeon->tiling_info.num_banks = 8;
+ break;
+ case 2:
+ radeon->tiling_info.num_banks = 16;
+ break;
+ default:
+ return -EINVAL;
+
+ }
switch ((tiling_config & 0xf00) >> 8) {
case 0:
static int radeon_drm_get_tiling(struct radeon *radeon)
{
- struct drm_radeon_info info;
+ struct drm_radeon_info info = {};
int r;
uint32_t tiling_config = 0;
static int radeon_get_clock_crystal_freq(struct radeon *radeon)
{
- struct drm_radeon_info info;
+ struct drm_radeon_info info = {};
uint32_t clock_crystal_freq;
int r;
- radeon->device = 0;
info.request = RADEON_INFO_CLOCK_CRYSTAL_FREQ;
info.value = (uintptr_t)&clock_crystal_freq;
r = drmCommandWriteRead(radeon->fd, DRM_RADEON_INFO, &info,
static int radeon_get_num_backends(struct radeon *radeon)
{
- struct drm_radeon_info info;
+ struct drm_radeon_info info = {};
uint32_t num_backends;
int r;
- radeon->device = 0;
info.request = RADEON_INFO_NUM_BACKENDS;
info.value = (uintptr_t)&num_backends;
r = drmCommandWriteRead(radeon->fd, DRM_RADEON_INFO, &info,
case CHIP_CYPRESS:
case CHIP_HEMLOCK:
case CHIP_PALM:
+ case CHIP_SUMO:
+ case CHIP_SUMO2:
case CHIP_BARTS:
case CHIP_TURKS:
case CHIP_CAICOS:
/* set default group bytes, overridden by tiling info ioctl */
radeon->tiling_info.group_bytes = 512;
break;
+ case CHIP_CAYMAN:
+ radeon->chip_class = CAYMAN;
+ /* set default group bytes, overridden by tiling info ioctl */
+ radeon->tiling_info.group_bytes = 512;
+ break;
default:
fprintf(stderr, "%s unknown or unsupported chipset 0x%04X\n",
__func__, radeon->device);