#ifndef R600_PRIV_H
#define R600_PRIV_H
-#include <errno.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <assert.h>
-#include <util/u_double_list.h>
-#include <util/u_inlines.h>
-#include "util/u_hash_table.h"
-#include <os/os_thread.h>
#include "r600.h"
+#include "../../radeon/drm/radeon_winsys.h"
+#include "util/u_hash_table.h"
+#include "os/os_thread.h"
+#include "radeon_drm.h"
#define PKT_COUNT_C 0xC000FFFF
#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
-struct r600_bomgr;
-struct r600_bo;
-
struct radeon {
- int fd;
- int refcount;
- unsigned device;
+ struct radeon_winsys *ws;
+ struct radeon_info info;
unsigned family;
enum chip_class chip_class;
struct r600_tiling_info tiling_info;
- struct r600_bomgr *bomgr;
- unsigned fence;
- unsigned *cfence;
- struct r600_bo *fence_bo;
- unsigned clock_crystal_freq;
- unsigned num_backends;
- unsigned minor_version;
-
- /* List of buffer handles and its mutex. */
- struct util_hash_table *bo_handles;
- pipe_mutex bo_handles_mutex;
};
+/* these flags are used in register flags and added into block flags */
#define REG_FLAG_NEED_BO 1
#define REG_FLAG_DIRTY_ALWAYS 2
#define REG_FLAG_RV6XX_SBU 4
+#define REG_FLAG_NOT_R600 8
+#define REG_FLAG_ENABLE_ALWAYS 16
+#define BLOCK_FLAG_RESOURCE 32
+#define REG_FLAG_FLUSH_CHANGE 64
struct r600_reg {
unsigned offset;
#define BO_BOUND_TEXTURE 1
struct radeon_bo {
struct pipe_reference reference;
+ struct pb_buffer *buf;
+ struct radeon_winsys_cs_handle *cs_buf;
unsigned handle;
unsigned size;
- unsigned alignment;
int map_count;
void *data;
- struct list_head fencedlist;
- unsigned fence;
- struct r600_context *ctx;
- boolean shared;
- struct r600_reloc *reloc;
- unsigned reloc_id;
+
unsigned last_flush;
- unsigned name;
unsigned binding;
};
struct r600_bo {
- struct pipe_reference reference;
- unsigned size;
- unsigned tiling_flags;
- unsigned kernel_pitch;
+ struct pipe_reference reference; /* this must be the first member for the r600_bo_reference inline to work */
+ /* DO NOT MOVE THIS ^ */
unsigned domains;
struct radeon_bo *bo;
- unsigned fence;
- /* manager data */
- struct list_head list;
- unsigned manager_id;
- unsigned alignment;
- unsigned offset;
- int64_t start;
- int64_t end;
};
-struct r600_bomgr {
- struct radeon *radeon;
- unsigned usecs;
- pipe_mutex mutex;
- struct list_head delayed;
- unsigned num_delayed;
-};
-
-/*
- * r600_drm.c
- */
-struct radeon *r600_new(int fd, unsigned device);
-void r600_delete(struct radeon *r600);
-
/*
* radeon_pciid.c
*/
* radeon_bo.c
*/
struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle,
- unsigned size, unsigned alignment);
+ unsigned size, unsigned alignment, unsigned bind, unsigned initial_domain);
void radeon_bo_reference(struct radeon *radeon, struct radeon_bo **dst,
struct radeon_bo *src);
int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo);
int radeon_bo_fencelist(struct radeon *radeon, struct radeon_bo **bolist, uint32_t num_bo);
int radeon_bo_get_tiling_flags(struct radeon *radeon,
struct radeon_bo *bo,
- uint32_t *tiling_flags,
- uint32_t *pitch);
+ uint32_t *tiling_flags);
int radeon_bo_get_name(struct radeon *radeon,
struct radeon_bo *bo,
uint32_t *name);
* r600_hw_context.c
*/
int r600_context_init_fence(struct r600_context *ctx);
-void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct r600_bo *rbo);
void r600_context_bo_flush(struct r600_context *ctx, unsigned flush_flags,
unsigned flush_mask, struct r600_bo *rbo);
struct r600_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned offset);
int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg,
unsigned opcode, unsigned offset_base);
-void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset);
+void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, struct r600_block *block);
void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block);
+void r600_context_block_resource_emit_dirty(struct r600_context *ctx, struct r600_block *block);
void r600_context_dirty_block(struct r600_context *ctx, struct r600_block *block,
int dirty, int index);
int r600_setup_block_table(struct r600_context *ctx);
void r600_context_reg(struct r600_context *ctx,
unsigned offset, unsigned value,
unsigned mask);
-/*
- * r600_bo.c
- */
-void r600_bo_destroy(struct radeon *radeon, struct r600_bo *bo);
+void r600_init_cs(struct r600_context *ctx);
+int r600_resource_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride, struct r600_reg *reg, int nreg, unsigned offset_base);
-/*
- * r600_bomgr.c
- */
-struct r600_bomgr *r600_bomgr_create(struct radeon *radeon, unsigned usecs);
-void r600_bomgr_destroy(struct r600_bomgr *mgr);
-bool r600_bomgr_bo_destroy(struct r600_bomgr *mgr, struct r600_bo *bo);
-void r600_bomgr_bo_init(struct r600_bomgr *mgr, struct r600_bo *bo);
-struct r600_bo *r600_bomgr_bo_create(struct r600_bomgr *mgr,
- unsigned size,
- unsigned alignment,
- unsigned cfence);
+static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_bo *rbo)
+{
+ struct radeon_bo *bo = rbo->bo;
+ unsigned reloc_index;
+
+ assert(bo != NULL);
+ reloc_index =
+ ctx->radeon->ws->cs_add_reloc(ctx->cs, bo->cs_buf, rbo->domains, rbo->domains);
+
+ if (reloc_index >= ctx->creloc)
+ ctx->creloc = reloc_index+1;
+
+ radeon_bo_reference(ctx->radeon, &ctx->bo[reloc_index], bo);
+ return reloc_index * 4;
+}
/*
- * helpers
+ * r600_bo.c
*/
+void r600_bo_destroy(struct radeon *radeon, struct r600_bo *bo);
-/* each range covers 9 bits of dword space = 512 dwords = 2k bytes */
-/* there is a block entry for each register so 512 blocks */
-/* we have no registers to read/write below 0x8000 (0x2000 in dw space) */
-/* we use some fake offsets at 0x40000 to do evergreen sampler borders so take 0x42000 as a max bound*/
-#define RANGE_OFFSET_START 0x8000
-#define HASH_SHIFT 9
-#define NUM_RANGES (0x42000 - RANGE_OFFSET_START) / (4 << HASH_SHIFT) /* 128 << 9 = 64k */
-
-#define CTX_RANGE_ID(ctx, offset) ((((offset - RANGE_OFFSET_START) >> 2) >> HASH_SHIFT) & 255)
-#define CTX_BLOCK_ID(ctx, offset) (((offset - RANGE_OFFSET_START) >> 2) & ((1 << HASH_SHIFT) - 1))
/*
* radeon_bo.c
/*
* fence
*/
-static inline bool fence_is_after(unsigned fence, unsigned ofence)
+static inline boolean fence_is_after(unsigned fence, unsigned ofence)
{
/* handle wrap around */
if (fence < 0x80000000 && ofence > 0x80000000)
projects / mesa.git / blobdiff