gallium/radeon: remove RADEON_FLAG_CPU_ACCESS

[mesa.git] / src / gallium / winsys / radeon / drm / radeon_drm_bo.c

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index 9bbf1b325012b884786e61d86c839e389a15aac2..283860d7a867af6d9fcd6e2b1f7d1bacdd4af709 100644 (file)
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -611,8 +611,6 @@ static struct radeon_bo *radeon_create_bo(struct radeon_drm_winsys *rws,
 
     if (flags & RADEON_FLAG_GTT_WC)
         args.flags |= RADEON_GEM_GTT_WC;
-    if (flags & RADEON_FLAG_CPU_ACCESS)
-        args.flags |= RADEON_GEM_CPU_ACCESS;
     if (flags & RADEON_FLAG_NO_CPU_ACCESS)
         args.flags |= RADEON_GEM_NO_CPU_ACCESS;
 
@@ -740,8 +738,6 @@ struct pb_slab *radeon_bo_slab_alloc(void *priv, unsigned heap,
 
     if (heap & 1)
         flags |= RADEON_FLAG_GTT_WC;
-    if (heap & 2)
-        flags |= RADEON_FLAG_CPU_ACCESS;
 
     switch (heap >> 2) {
     case 0:
@@ -943,7 +939,7 @@ radeon_winsys_bo_create(struct radeon_winsys *rws,
         return NULL;
 
     /* Sub-allocate small buffers from slabs. */
-    if (!(flags & RADEON_FLAG_HANDLE) &&
+    if (!(flags & RADEON_FLAG_NO_SUBALLOC) &&
         size <= (1 << RADEON_SLAB_MAX_SIZE_LOG2) &&
         ws->info.has_virtual_memory &&
         alignment <= MAX2(1 << RADEON_SLAB_MIN_SIZE_LOG2, util_next_power_of_two(size))) {
@@ -952,9 +948,7 @@ radeon_winsys_bo_create(struct radeon_winsys *rws,
 
         if (flags & RADEON_FLAG_GTT_WC)
             heap |= 1;
-        if (flags & RADEON_FLAG_CPU_ACCESS)
-            heap |= 2;
-        if (flags & ~(RADEON_FLAG_GTT_WC | RADEON_FLAG_CPU_ACCESS))
+        if (flags & ~RADEON_FLAG_GTT_WC)
             goto no_slab;
 
         switch (domain) {
@@ -991,7 +985,7 @@ radeon_winsys_bo_create(struct radeon_winsys *rws,
 no_slab:
 
     /* This flag is irrelevant for the cache. */
-    flags &= ~RADEON_FLAG_HANDLE;
+    flags &= ~RADEON_FLAG_NO_SUBALLOC;
 
     /* Align size to page size. This is the minimum alignment for normal
      * BOs. Aligning this here helps the cached bufmgr. Especially small BOs,
@@ -1027,7 +1021,8 @@ no_slab:
                           pb_cache_bucket);
     if (!bo) {
         /* Clear the cache and try again. */
-        pb_slabs_reclaim(&ws->bo_slabs);
+        if (ws->info.has_virtual_memory)
+            pb_slabs_reclaim(&ws->bo_slabs);
         pb_cache_release_all_buffers(&ws->bo_cache);
         bo = radeon_create_bo(ws, size, alignment, usage, domain, flags,
                               pb_cache_bucket);
@@ -1289,10 +1284,9 @@ static bool radeon_winsys_bo_get_handle(struct pb_buffer *buffer,
     struct radeon_bo *bo = radeon_bo(buffer);
     struct radeon_drm_winsys *ws = bo->rws;
 
-    if (!bo->handle) {
-        offset += bo->va - bo->u.slab.real->va;
-        bo = bo->u.slab.real;
-    }
+    /* Don't allow exports of slab entries. */
+    if (!bo->handle)
+        return false;
 
     memset(&flink, 0, sizeof(flink));