r300g: cache tiling flags to reduce the number of DRM calls

[mesa.git] / src / gallium / winsys / radeon / drm / radeon_drm_buffer.c

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_buffer.c b/src/gallium/winsys/radeon/drm/radeon_drm_buffer.c
index 5fd20cc7754f06d3ca7919f948b2bcf292c46b67..b8366498922803844b3d895e23242e8caf5e1ee1 100644 (file)
--- a/src/gallium/winsys/radeon/drm/radeon_drm_buffer.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_buffer.c
@@ -22,6 +22,8 @@ struct radeon_drm_buffer {
 
     boolean flinked;
     uint32_t flink;
+    uint32_t tileflags;
+    uint32_t pitch;
 
     struct radeon_drm_buffer *next, *prev;
 };
@@ -72,9 +74,9 @@ radeon_drm_buffer_map(struct pb_buffer *_buf,
     struct radeon_drm_buffer *buf = radeon_drm_buffer(_buf);
     int write = 0;
 
-    if (flags & PIPE_BUFFER_USAGE_DONTBLOCK) {
-       if ((_buf->base.usage & PIPE_BUFFER_USAGE_VERTEX) ||
-           (_buf->base.usage & PIPE_BUFFER_USAGE_INDEX))
+    if (flags & PIPE_TRANSFER_DONTBLOCK) {
+       if ((_buf->base.usage & PIPE_BIND_VERTEX_BUFFER) ||
+           (_buf->base.usage & PIPE_BIND_INDEX_BUFFER))
            if (radeon_bo_is_referenced_by_cs(buf->bo, buf->mgr->rws->cs))
                return NULL;
     }
@@ -82,7 +84,7 @@ radeon_drm_buffer_map(struct pb_buffer *_buf,
     if (buf->bo->ptr != NULL)
        return buf->bo->ptr;
 
-    if (flags & PIPE_BUFFER_USAGE_DONTBLOCK) {
+    if (flags & PIPE_TRANSFER_DONTBLOCK) {
         uint32_t domain;
         if (radeon_bo_is_busy(buf->bo, &domain))
             return NULL;
@@ -92,7 +94,7 @@ radeon_drm_buffer_map(struct pb_buffer *_buf,
         buf->mgr->rws->flush_cb(buf->mgr->rws->flush_data);
     }
 
-    if (flags & PIPE_BUFFER_USAGE_CPU_WRITE) {
+    if (flags & PIPE_TRANSFER_WRITE) {
         write = 1;
     }
 
@@ -148,16 +150,20 @@ static uint32_t radeon_domain_from_usage(unsigned usage)
 {
     uint32_t domain = 0;
 
-    if (usage & PIPE_BUFFER_USAGE_GPU_WRITE) {
+    if (usage & PIPE_BIND_RENDER_TARGET) {
         domain |= RADEON_GEM_DOMAIN_VRAM;
     }
-    if (usage & PIPE_BUFFER_USAGE_PIXEL) {
+    if (usage & PIPE_BIND_DEPTH_STENCIL) {
         domain |= RADEON_GEM_DOMAIN_VRAM;
     }
-    if (usage & PIPE_BUFFER_USAGE_VERTEX) {
+    if (usage & PIPE_BIND_SAMPLER_VIEW) {
+        domain |= RADEON_GEM_DOMAIN_VRAM;
+    }
+    /* also need BIND_BLIT_SOURCE/DESTINATION ? */
+    if (usage & PIPE_BIND_VERTEX_BUFFER) {
         domain |= RADEON_GEM_DOMAIN_GTT;
     }
-    if (usage & PIPE_BUFFER_USAGE_INDEX) {
+    if (usage & PIPE_BIND_INDEX_BUFFER) {
         domain |= RADEON_GEM_DOMAIN_GTT;
     }
 
@@ -187,7 +193,7 @@ struct pb_buffer *radeon_drm_bufmgr_create_buffer_from_handle(struct pb_manager
 
     pipe_reference_init(&buf->base.base.reference, 1);
     buf->base.base.alignment = 0;
-    buf->base.base.usage = PIPE_BUFFER_USAGE_PIXEL;
+    buf->base.base.usage = PIPE_BIND_SAMPLER_VIEW;
     buf->base.base.size = 0;
     buf->base.vtbl = &radeon_drm_buffer_vtbl;
     buf->mgr = mgr;
@@ -314,6 +320,9 @@ void radeon_drm_bufmgr_get_tiling(struct pb_buffer *_buf,
 
     radeon_bo_get_tiling(buf->bo, &flags, &pitch);
 
+    buf->tileflags = flags;
+    buf->pitch = pitch;
+
     *microtiled = R300_BUFFER_LINEAR;
     *macrotiled = R300_BUFFER_LINEAR;
     if (flags & RADEON_BO_FLAGS_MICRO_TILE)
@@ -329,7 +338,7 @@ void radeon_drm_bufmgr_set_tiling(struct pb_buffer *_buf,
                                   uint32_t pitch)
 {
     struct radeon_drm_buffer *buf = get_drm_buffer(_buf);
-    uint32_t flags = 0, old_flags, old_pitch;
+    uint32_t flags = 0;
     if (microtiled == R300_BUFFER_TILED)
         flags |= RADEON_BO_FLAGS_MICRO_TILE;
 /* XXX Remove this ifdef when libdrm version 2.4.19 becomes mandatory. */
@@ -340,17 +349,15 @@ void radeon_drm_bufmgr_set_tiling(struct pb_buffer *_buf,
     if (macrotiled == R300_BUFFER_TILED)
         flags |= RADEON_BO_FLAGS_MACRO_TILE;
 
-    radeon_bo_get_tiling(buf->bo, &old_flags, &old_pitch);
-
-    if (flags != old_flags || pitch != old_pitch) {
+    if (flags != buf->tileflags || pitch != buf->pitch) {
         /* Tiling determines how DRM treats the buffer data.
          * We must flush CS when changing it if the buffer is referenced. */
         if (radeon_bo_is_referenced_by_cs(buf->bo,  buf->mgr->rws->cs)) {
            buf->mgr->rws->flush_cb(buf->mgr->rws->flush_data);
         }
-    }
-    radeon_bo_set_tiling(buf->bo, flags, pitch);
 
+        radeon_bo_set_tiling(buf->bo, flags, pitch);
+    }
 }
 
 boolean radeon_drm_bufmgr_add_buffer(struct pb_buffer *_buf,
@@ -377,13 +384,25 @@ void radeon_drm_bufmgr_write_reloc(struct pb_buffer *_buf,
     }
 }
 
-boolean radeon_drm_bufmgr_is_buffer_referenced(struct pb_buffer *_buf)
+boolean radeon_drm_bufmgr_is_buffer_referenced(struct pb_buffer *_buf,
+                                               enum r300_reference_domain domain)
 {
     struct radeon_drm_buffer *buf = get_drm_buffer(_buf);
-    uint32_t domain;
+    uint32_t tmp;
+
+    if (domain & R300_REF_CS) {
+        if (radeon_bo_is_referenced_by_cs(buf->bo, buf->mgr->rws->cs)) {
+            return TRUE;
+        }
+    }
+
+    if (domain & R300_REF_HW) {
+        if (radeon_bo_is_busy(buf->bo, &tmp)) {
+            return TRUE;
+        }
+    }
 
-    return (radeon_bo_is_referenced_by_cs(buf->bo, buf->mgr->rws->cs) ||
-           radeon_bo_is_busy(buf->bo, &domain));
+    return FALSE;
 }