#include <xf86drm.h>
#include <stdio.h>
+/*
+ * this are copy from radeon_drm, once an updated libdrm is released
+ * we should bump configure.ac requirement for it and remove the following
+ * field
+ */
+#ifndef RADEON_INFO_TILING_CONFIG
+#define RADEON_INFO_TILING_CONFIG 6
+#endif
+
#ifndef RADEON_INFO_WANT_HYPERZ
#define RADEON_INFO_WANT_HYPERZ 7
#endif
+
#ifndef RADEON_INFO_WANT_CMASK
#define RADEON_INFO_WANT_CMASK 8
#endif
+#ifndef RADEON_INFO_CLOCK_CRYSTAL_FREQ
+#define RADEON_INFO_CLOCK_CRYSTAL_FREQ 9
+#endif
+
+#ifndef RADEON_INFO_NUM_BACKENDS
+#define RADEON_INFO_NUM_BACKENDS 0xa
+#endif
+
+#ifndef RADEON_INFO_NUM_TILE_PIPES
+#define RADEON_INFO_NUM_TILE_PIPES 0xb
+#endif
+
+#ifndef RADEON_INFO_BACKEND_MAP
+#define RADEON_INFO_BACKEND_MAP 0xd
+#endif
+
+#ifndef RADEON_INFO_VA_START
+/* virtual address start, va < start are reserved by the kernel */
+#define RADEON_INFO_VA_START 0x0e
+/* maximum size of ib using the virtual memory cs */
+#define RADEON_INFO_IB_VM_MAX_SIZE 0x0f
+#endif
+
+
/* Enable/disable feature access for one command stream.
* If enable == TRUE, return TRUE on success.
* Otherwise, return FALSE.
pipe_mutex *mutex,
unsigned request, boolean enable)
{
- struct drm_radeon_info info = {0};
+ struct drm_radeon_info info;
unsigned value = enable ? 1 : 0;
+ memset(&info, 0, sizeof(info));
+
pipe_mutex_lock(*mutex);
/* Early exit if we are sure the request will fail. */
}
static boolean radeon_get_drm_value(int fd, unsigned request,
- const char *name, uint32_t *out)
+ const char *errname, uint32_t *out)
{
- struct drm_radeon_info info = {0};
+ struct drm_radeon_info info;
int retval;
+ memset(&info, 0, sizeof(info));
+
info.value = (unsigned long)out;
info.request = request;
retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info));
if (retval) {
- fprintf(stderr, "%s: Failed to get %s, error number %d\n",
- __func__, name, retval);
+ if (errname) {
+ fprintf(stderr, "radeon: Failed to get %s, error number %d\n",
+ errname, retval);
+ }
return FALSE;
}
return TRUE;
/* Helper function to do the ioctls needed for setup and init. */
static boolean do_winsys_init(struct radeon_drm_winsys *ws)
{
- struct drm_radeon_gem_info gem_info = {0};
+ struct drm_radeon_gem_info gem_info;
int retval;
drmVersionPtr version;
+ memset(&gem_info, 0, sizeof(gem_info));
+
/* We do things in a specific order here.
*
* DRM version first. We need to be sure we're running on a KMS chipset.
#define CHIPSET(pci_id, name, family) case pci_id:
#include "pci_ids/r300_pci_ids.h"
#undef CHIPSET
+ ws->gen = R300;
+ break;
+
+#define CHIPSET(pci_id, name, family) case pci_id:
+#include "pci_ids/r600_pci_ids.h"
+#undef CHIPSET
+ ws->gen = R600;
break;
default:
retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO,
&gem_info, sizeof(gem_info));
if (retval) {
- fprintf(stderr, "%s: Failed to get MM info, error number %d\n",
- __FUNCTION__, retval);
+ fprintf(stderr, "radeon: Failed to get MM info, error number %d\n",
+ retval);
return FALSE;
}
ws->info.gart_size = gem_info.gart_size;
ws->num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
/* Generation-specific queries. */
- if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_GB_PIPES,
- "GB pipe count",
- &ws->info.r300_num_gb_pipes))
- return FALSE;
+ if (ws->gen == R300) {
+ if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_GB_PIPES,
+ "GB pipe count",
+ &ws->info.r300_num_gb_pipes))
+ return FALSE;
- if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_Z_PIPES,
- "Z pipe count",
- &ws->info.r300_num_z_pipes))
- return FALSE;
+ if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_Z_PIPES,
+ "Z pipe count",
+ &ws->info.r300_num_z_pipes))
+ return FALSE;
+ }
+ else if (ws->gen == R600) {
+ if (ws->info.drm_minor >= 9 &&
+ !radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
+ "num backends",
+ &ws->info.r600_num_backends))
+ return FALSE;
+
+ /* get the GPU counter frequency, failure is not fatal */
+ radeon_get_drm_value(ws->fd, RADEON_INFO_CLOCK_CRYSTAL_FREQ, NULL,
+ &ws->info.r600_clock_crystal_freq);
+
+ radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL,
+ &ws->info.r600_tiling_config);
+
+ if (ws->info.drm_minor >= 11) {
+ radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL,
+ &ws->info.r600_num_tile_pipes);
+
+ if (radeon_get_drm_value(ws->fd, RADEON_INFO_BACKEND_MAP, NULL,
+ &ws->info.r600_backend_map))
+ ws->info.r600_backend_map_valid = TRUE;
+ }
+ ws->info.r600_virtual_address = FALSE;
+ if (ws->info.drm_minor >= 13) {
+ ws->info.r600_virtual_address = TRUE;
+ if (!radeon_get_drm_value(ws->fd, RADEON_INFO_VA_START, NULL,
+ &ws->info.r600_va_start))
+ ws->info.r600_virtual_address = FALSE;
+ if (!radeon_get_drm_value(ws->fd, RADEON_INFO_IB_VM_MAX_SIZE, NULL,
+ &ws->info.r600_ib_vm_max_size))
+ ws->info.r600_virtual_address = FALSE;
+ }
+ }
return TRUE;
}
ws->cman->destroy(ws->cman);
ws->kman->destroy(ws->kman);
+ if (ws->gen == R600) {
+ radeon_surface_manager_free(ws->surf_man);
+ }
FREE(rws);
}
struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
switch (fid) {
- case RADEON_FID_HYPERZ_RAM_ACCESS:
+ case RADEON_FID_R300_HYPERZ_ACCESS:
if (debug_get_bool_option("RADEON_HYPERZ", FALSE)) {
return radeon_set_fd_access(cs, &cs->ws->hyperz_owner,
&cs->ws->hyperz_owner_mutex,
return FALSE;
}
- case RADEON_FID_CMASK_RAM_ACCESS:
+ case RADEON_FID_R300_CMASK_ACCESS:
if (debug_get_bool_option("RADEON_CMASK", FALSE)) {
return radeon_set_fd_access(cs, &cs->ws->cmask_owner,
&cs->ws->cmask_owner_mutex,
return FALSE;
}
+static int radeon_drm_winsys_surface_init(struct radeon_winsys *rws,
+ struct radeon_surface *surf)
+{
+ struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
+
+ return radeon_surface_init(ws->surf_man, surf);
+}
+
+static int radeon_drm_winsys_surface_best(struct radeon_winsys *rws,
+ struct radeon_surface *surf)
+{
+ struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
+
+ return radeon_surface_best(ws->surf_man, surf);
+}
+
struct radeon_winsys *radeon_drm_winsys_create(int fd)
{
struct radeon_drm_winsys *ws = CALLOC_STRUCT(radeon_drm_winsys);
/* Create managers. */
ws->kman = radeon_bomgr_create(ws);
if (!ws->kman)
- goto fail;
+ goto fail;
ws->cman = pb_cache_manager_create(ws->kman, 1000000);
if (!ws->cman)
- goto fail;
+ goto fail;
+
+ /* FIXME check for libdrm version ?? */
+ if (ws->gen == R600) {
+ ws->surf_man = radeon_surface_manager_new(fd);
+ if (!ws->surf_man)
+ goto fail;
+ }
/* Set functions. */
ws->base.destroy = radeon_winsys_destroy;
ws->base.query_info = radeon_query_info;
ws->base.cs_request_feature = radeon_cs_request_feature;
+ ws->base.surface_init = radeon_drm_winsys_surface_init;
+ ws->base.surface_best = radeon_drm_winsys_surface_best;
radeon_bomgr_init_functions(ws);
radeon_drm_cs_init_functions(ws);
fail:
if (ws->cman)
- ws->cman->destroy(ws->cman);
+ ws->cman->destroy(ws->cman);
if (ws->kman)
- ws->kman->destroy(ws->kman);
+ ws->kman->destroy(ws->kman);
+ if (ws->surf_man)
+ radeon_surface_manager_free(ws->surf_man);
FREE(ws);
return NULL;
}
projects / mesa.git / blobdiff