util: remove LIST_ADDTAIL macro

[mesa.git] / src / gallium / winsys / radeon / drm / radeon_drm_winsys.c

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 225cc01a33d81dd82c9809b3df19c12e620b72b9..36d506b4928099512be65e5bfcd7dbc31fe1db6f 100644 (file)
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -166,6 +166,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
     ws->info.drm_major = version->version_major;
     ws->info.drm_minor = version->version_minor;
     ws->info.drm_patchlevel = version->version_patchlevel;
+    ws->info.is_amdgpu = false;
     drmFreeVersion(version);
 
     /* Get PCI ID. */
@@ -275,7 +276,6 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
     case CHIP_KAVERI:
     case CHIP_KABINI:
     case CHIP_HAWAII:
-    case CHIP_MULLINS:
         ws->info.chip_class = GFX7;
         break;
     }
@@ -296,7 +296,6 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
     case CHIP_ARUBA:
     case CHIP_KAVERI:
     case CHIP_KABINI:
-    case CHIP_MULLINS:
        ws->info.has_dedicated_vram = false;
        break;
 
@@ -482,7 +481,6 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
     switch (ws->info.family) {
     case CHIP_HAINAN:
     case CHIP_KABINI:
-    case CHIP_MULLINS:
         ws->info.num_tcc_blocks = 2;
         break;
     case CHIP_VERDE:
@@ -572,8 +570,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
                                              ws->info.drm_minor >= 38;
     ws->info.si_TA_CS_BC_BASE_ADDR_allowed = ws->info.drm_minor >= 48;
     ws->info.has_bo_metadata = false;
-    ws->info.has_gpu_reset_status_query = false;
-    ws->info.has_gpu_reset_counter_query = ws->info.drm_minor >= 43;
+    ws->info.has_gpu_reset_status_query = ws->info.drm_minor >= 43;
     ws->info.has_eqaa_surface_allocator = false;
     ws->info.has_format_bc1_through_bc7 = ws->info.drm_minor >= 31;
     ws->info.kernel_flushes_tc_l2_after_ib = true;
@@ -590,8 +587,14 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
     ws->info.has_2d_tiling = ws->info.chip_class <= GFX6 || ws->info.drm_minor >= 35;
     ws->info.has_read_registers_query = ws->info.drm_minor >= 42;
     ws->info.max_alignment = 1024*1024;
+    ws->info.has_graphics = true;
+    ws->info.cpdma_prefetch_writes_memory = true;
+    ws->info.max_wave64_per_simd = 10;
+    ws->info.num_physical_sgprs_per_simd = 512;
+    ws->info.num_physical_wave64_vgprs_per_simd = 256;
 
-    ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;
+    ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL ||
+                   strstr(debug_get_option("AMD_DEBUG", ""), "check_vm") != NULL;
 
     return true;
 }
@@ -656,6 +659,18 @@ static bool radeon_cs_request_feature(struct radeon_cmdbuf *rcs,
     return false;
 }
 
+uint32_t radeon_drm_get_gpu_reset_counter(struct radeon_drm_winsys *ws)
+{
+    uint64_t retval = 0;
+
+    if (!ws->info.has_gpu_reset_status_query)
+        return 0;
+
+    radeon_get_drm_value(ws->fd, RADEON_INFO_GPU_RESET_COUNTER,
+                         "gpu-reset-counter", (uint32_t*)&retval);
+    return retval;
+}
+
 static uint64_t radeon_query_value(struct radeon_winsys *rws,
                                    enum radeon_value_id value)
 {
@@ -718,10 +733,6 @@ static uint64_t radeon_query_value(struct radeon_winsys *rws,
         radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_MCLK,
                              "current-gpu-mclk", (uint32_t*)&retval);
         return retval;
-    case RADEON_GPU_RESET_COUNTER:
-        radeon_get_drm_value(ws->fd, RADEON_INFO_GPU_RESET_COUNTER,
-                             "gpu-reset-counter", (uint32_t*)&retval);
-        return retval;
     case RADEON_CS_THREAD_TIME:
         return util_queue_get_thread_time_nano(&ws->cs_queue, 0);
     }