#define RADEON_INFO_ACTIVE_CU_COUNT 0x20
#endif
+#ifndef RADEON_INFO_CURRENT_GPU_TEMP
+#define RADEON_INFO_CURRENT_GPU_TEMP 0x21
+#define RADEON_INFO_CURRENT_GPU_SCLK 0x22
+#define RADEON_INFO_CURRENT_GPU_MCLK 0x23
+#define RADEON_INFO_READ_REG 0x24
+#endif
+
static struct util_hash_table *fd_tab = NULL;
pipe_static_mutex(fd_tab_mutex);
if (enable) {
if (value) {
*owner = applier;
- printf("radeon: Acquired access to %s.\n", request_name);
pipe_mutex_unlock(*mutex);
return TRUE;
}
} else {
*owner = NULL;
- printf("radeon: Released access to %s.\n", request_name);
}
pipe_mutex_unlock(*mutex);
}
}
+ /* Check for userptr support. */
+ {
+ struct drm_radeon_gem_userptr args = {0};
+
+ /* If the ioctl doesn't exist, -EINVAL is returned.
+ *
+ * If the ioctl exists, it should return -EACCES
+ * if RADEON_GEM_USERPTR_READONLY or RADEON_GEM_USERPTR_REGISTER
+ * aren't set.
+ */
+ ws->info.has_userptr =
+ drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_USERPTR,
+ &args, sizeof(args)) == -EACCES;
+ }
+
/* Get GEM info. */
retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO,
&gem_info, sizeof(gem_info));
&ws->info.max_sclk);
ws->info.max_sclk /= 1000;
+ radeon_get_drm_value(ws->fd, RADEON_INFO_SI_BACKEND_ENABLED_MASK, NULL,
+ &ws->info.si_backend_enabled_mask);
+
ws->num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
/* Generation-specific queries. */
radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_PIPES, NULL,
&ws->info.r600_max_pipes);
+ /* All GPUs have at least one compute unit */
+ ws->info.max_compute_units = 1;
radeon_get_drm_value(ws->fd, RADEON_INFO_ACTIVE_CU_COUNT, NULL,
&ws->info.max_compute_units);
pipe_mutex_destroy(ws->cmask_owner_mutex);
pipe_mutex_destroy(ws->cs_stack_lock);
- ws->cman_vram->destroy(ws->cman_vram);
- ws->cman_vram_gtt_wc->destroy(ws->cman_vram_gtt_wc);
- ws->cman_gtt->destroy(ws->cman_gtt);
- ws->cman_gtt_wc->destroy(ws->cman_gtt_wc);
+ ws->cman->destroy(ws->cman);
ws->kman->destroy(ws->kman);
if (ws->gen >= DRV_R600) {
radeon_surface_manager_free(ws->surf_man);
radeon_get_drm_value(ws->fd, RADEON_INFO_GTT_USAGE,
"gtt-usage", (uint32_t*)&retval);
return retval;
+ case RADEON_GPU_TEMPERATURE:
+ radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_TEMP,
+ "gpu-temp", (uint32_t*)&retval);
+ return retval;
+ case RADEON_CURRENT_SCLK:
+ radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_SCLK,
+ "current-gpu-sclk", (uint32_t*)&retval);
+ return retval;
+ case RADEON_CURRENT_MCLK:
+ radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_MCLK,
+ "current-gpu-mclk", (uint32_t*)&retval);
+ return retval;
}
return 0;
}
ws->kman = radeon_bomgr_create(ws);
if (!ws->kman)
goto fail;
- ws->cman_vram = pb_cache_manager_create(ws->kman, 1000000, 2.0f, 0,
- ws->info.vram_size / 8);
- if (!ws->cman_vram)
- goto fail;
- ws->cman_vram_gtt_wc = pb_cache_manager_create(ws->kman, 1000000, 2.0f, 0,
- ws->info.vram_size / 8);
- if (!ws->cman_vram_gtt_wc)
- goto fail;
- ws->cman_gtt = pb_cache_manager_create(ws->kman, 1000000, 2.0f, 0,
- ws->info.gart_size / 8);
- if (!ws->cman_gtt)
- goto fail;
- ws->cman_gtt_wc = pb_cache_manager_create(ws->kman, 1000000, 2.0f, 0,
- ws->info.gart_size / 8);
- if (!ws->cman_gtt_wc)
+
+ ws->cman = pb_cache_manager_create(ws->kman, 1000000, 2.0f, 0,
+ MIN2(ws->info.vram_size, ws->info.gart_size));
+ if (!ws->cman)
goto fail;
if (ws->gen >= DRV_R600) {
fail:
pipe_mutex_unlock(fd_tab_mutex);
- if (ws->cman_gtt)
- ws->cman_gtt->destroy(ws->cman_gtt);
- if (ws->cman_gtt_wc)
- ws->cman_gtt_wc->destroy(ws->cman_gtt_wc);
- if (ws->cman_vram)
- ws->cman_vram->destroy(ws->cman_vram);
- if (ws->cman_vram_gtt_wc)
- ws->cman_vram_gtt_wc->destroy(ws->cman_vram_gtt_wc);
+ if (ws->cman)
+ ws->cman->destroy(ws->cman);
if (ws->kman)
ws->kman->destroy(ws->kman);
if (ws->surf_man)