* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
-/*
- * Authors:
- * Corbin Simpson <MostAwesomeDude@gmail.com>
- * Joakim Sindholt <opensource@zhasha.com>
- * Marek Olšák <maraeo@gmail.com>
- */
#include "radeon_drm_bo.h"
#include "radeon_drm_cs.h"
/* Early exit if we are sure the request will fail. */
if (enable) {
if (*owner) {
- pipe_mutex_unlock(*mutex);
+ mtx_unlock(&*mutex);
return false;
}
} else {
if (*owner != applier) {
- pipe_mutex_unlock(*mutex);
+ mtx_unlock(&*mutex);
return false;
}
}
info.request = request;
if (drmCommandWriteRead(applier->ws->fd, DRM_RADEON_INFO,
&info, sizeof(info)) != 0) {
- pipe_mutex_unlock(*mutex);
+ mtx_unlock(&*mutex);
return false;
}
if (enable) {
if (value) {
*owner = applier;
- pipe_mutex_unlock(*mutex);
+ mtx_unlock(&*mutex);
return true;
}
} else {
*owner = NULL;
}
- pipe_mutex_unlock(*mutex);
+ mtx_unlock(&*mutex);
return false;
}
#include "pci_ids/r600_pci_ids.h"
#undef CHIPSET
-#define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_SI; break;
+#define CHIPSET(pci_id, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_SI; break;
#include "pci_ids/radeonsi_pci_ids.h"
#undef CHIPSET
}
/* Check for dma */
- ws->info.has_sdma = false;
+ ws->info.num_sdma_rings = 0;
/* DMA is disabled on R700. There is IB corruption and hangs. */
if (ws->info.chip_class >= EVERGREEN && ws->info.drm_minor >= 27) {
- ws->info.has_sdma = true;
+ ws->info.num_sdma_rings = 1;
}
/* Check for UVD and VCE */
- ws->info.has_uvd = false;
+ ws->info.has_hw_decode = false;
ws->info.vce_fw_version = 0x00000000;
if (ws->info.drm_minor >= 32) {
uint32_t value = RADEON_CS_RING_UVD;
if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
"UVD Ring working", &value))
- ws->info.has_uvd = value;
+ ws->info.has_hw_decode = value;
value = RADEON_CS_RING_VCE;
if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
/* Radeon allocates all buffers as contigous, which makes large allocations
* unlikely to succeed. */
ws->info.max_alloc_size = MAX2(ws->info.vram_size, ws->info.gart_size) * 0.7;
+ if (ws->info.has_dedicated_vram)
+ ws->info.max_alloc_size = MIN2(ws->info.vram_size * 0.7, ws->info.max_alloc_size);
if (ws->info.drm_minor < 40)
ws->info.max_alloc_size = MIN2(ws->info.max_alloc_size, 256*1024*1024);
+ /* Both 32-bit and 64-bit address spaces only have 4GB. */
+ ws->info.max_alloc_size = MIN2(ws->info.max_alloc_size, 3ull*1024*1024*1024);
/* Get max clock frequency info and convert it to MHz */
radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SCLK, NULL,
&ws->info.max_shader_clock);
ws->info.max_shader_clock /= 1000;
- /* Default value. */
- ws->info.enabled_rb_mask = u_bit_consecutive(0, ws->info.num_render_backends);
- /* This fails on non-GCN or older kernels: */
- radeon_get_drm_value(ws->fd, RADEON_INFO_SI_BACKEND_ENABLED_MASK, NULL,
- &ws->info.enabled_rb_mask);
-
ws->num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
/* Generation-specific queries. */
&ws->info.r600_gb_backend_map))
ws->info.r600_gb_backend_map_valid = true;
- ws->info.has_virtual_memory = false;
+ /* Default value. */
+ ws->info.enabled_rb_mask = u_bit_consecutive(0, ws->info.num_render_backends);
+ /*
+ * This fails (silently) on non-GCN or older kernels, overwriting the
+ * default enabled_rb_mask with the result of the last query.
+ */
+ if (ws->gen >= DRV_SI)
+ radeon_get_drm_value(ws->fd, RADEON_INFO_SI_BACKEND_ENABLED_MASK, NULL,
+ &ws->info.enabled_rb_mask);
+
+ ws->info.r600_has_virtual_memory = false;
if (ws->info.drm_minor >= 13) {
uint32_t ib_vm_max_size;
- ws->info.has_virtual_memory = true;
+ ws->info.r600_has_virtual_memory = true;
if (!radeon_get_drm_value(ws->fd, RADEON_INFO_VA_START, NULL,
&ws->va_start))
- ws->info.has_virtual_memory = false;
+ ws->info.r600_has_virtual_memory = false;
if (!radeon_get_drm_value(ws->fd, RADEON_INFO_IB_VM_MAX_SIZE, NULL,
&ib_vm_max_size))
- ws->info.has_virtual_memory = false;
+ ws->info.r600_has_virtual_memory = false;
radeon_get_drm_value(ws->fd, RADEON_INFO_VA_UNMAP_WORKING, NULL,
&ws->va_unmap_working);
}
if (ws->gen == DRV_R600 && !debug_get_bool_option("RADEON_VA", false))
- ws->info.has_virtual_memory = false;
+ ws->info.r600_has_virtual_memory = false;
}
/* Get max pipes, this is only needed for compute shaders. All evergreen+
(ws->info.family == CHIP_HAWAII &&
ws->accel_working2 < 3);
ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */
+ ws->info.ib_start_alignment = 4096;
+ ws->info.kernel_flushes_hdp_before_ib = ws->info.drm_minor >= 40;
+ /* HTILE is broken with 1D tiling on old kernels and CIK. */
+ ws->info.htile_cmask_support_1d_tiling = ws->info.chip_class != CIK ||
+ ws->info.drm_minor >= 38;
+ ws->info.si_TA_CS_BC_BASE_ADDR_allowed = ws->info.drm_minor >= 48;
+ ws->info.has_bo_metadata = false;
ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;
mtx_destroy(&ws->hyperz_owner_mutex);
mtx_destroy(&ws->cmask_owner_mutex);
- if (ws->info.has_virtual_memory)
+ if (ws->info.r600_has_virtual_memory)
pb_slabs_deinit(&ws->bo_slabs);
pb_cache_deinit(&ws->bo_cache);
util_hash_table_destroy(ws->bo_handles);
util_hash_table_destroy(ws->bo_vas);
mtx_destroy(&ws->bo_handles_mutex);
- mtx_destroy(&ws->bo_va_mutex);
+ mtx_destroy(&ws->vm32.mutex);
+ mtx_destroy(&ws->vm64.mutex);
mtx_destroy(&ws->bo_fence_lock);
if (ws->fd >= 0)
"num-bytes-moved", (uint32_t*)&retval);
return retval;
case RADEON_NUM_EVICTIONS:
+ case RADEON_NUM_VRAM_CPU_PAGE_FAULTS:
case RADEON_VRAM_VIS_USAGE:
+ case RADEON_GFX_BO_LIST_COUNTER:
+ case RADEON_GFX_IB_SIZE_COUNTER:
return 0; /* unimplemented */
case RADEON_VRAM_USAGE:
radeon_get_drm_value(ws->fd, RADEON_INFO_VRAM_USAGE,
mtx_lock(&fd_tab_mutex);
destroy = pipe_reference(&rws->reference, NULL);
- if (destroy && fd_tab)
+ if (destroy && fd_tab) {
util_hash_table_remove(fd_tab, intptr_to_pointer(rws->fd));
+ if (util_hash_table_count(fd_tab) == 0) {
+ util_hash_table_destroy(fd_tab);
+ fd_tab = NULL;
+ }
+ }
- pipe_mutex_unlock(fd_tab_mutex);
+ mtx_unlock(&fd_tab_mutex);
return destroy;
}
}
PUBLIC struct radeon_winsys *
-radeon_drm_winsys_create(int fd, radeon_screen_create_t screen_create)
+radeon_drm_winsys_create(int fd, const struct pipe_screen_config *config,
+ radeon_screen_create_t screen_create)
{
struct radeon_drm_winsys *ws;
ws = util_hash_table_get(fd_tab, intptr_to_pointer(fd));
if (ws) {
pipe_reference(NULL, &ws->reference);
- pipe_mutex_unlock(fd_tab_mutex);
+ mtx_unlock(&fd_tab_mutex);
return &ws->base;
}
ws = CALLOC_STRUCT(radeon_drm_winsys);
if (!ws) {
- pipe_mutex_unlock(fd_tab_mutex);
+ mtx_unlock(&fd_tab_mutex);
return NULL;
}
if (!do_winsys_init(ws))
goto fail1;
- pb_cache_init(&ws->bo_cache, 500000, ws->check_vm ? 1.0f : 2.0f, 0,
+ pb_cache_init(&ws->bo_cache, RADEON_MAX_CACHED_HEAPS,
+ 500000, ws->check_vm ? 1.0f : 2.0f, 0,
MIN2(ws->info.vram_size, ws->info.gart_size),
radeon_bo_destroy,
radeon_bo_can_reclaim);
- if (ws->info.has_virtual_memory) {
+ if (ws->info.r600_has_virtual_memory) {
/* There is no fundamental obstacle to using slab buffer allocation
* without GPUVM, but enabling it requires making sure that the drivers
* honor the address offset.
*/
if (!pb_slabs_init(&ws->bo_slabs,
RADEON_SLAB_MIN_SIZE_LOG2, RADEON_SLAB_MAX_SIZE_LOG2,
- 12,
+ RADEON_MAX_SLAB_HEAPS,
ws,
radeon_bo_can_reclaim_slab,
radeon_bo_slab_alloc,
ws->bo_handles = util_hash_table_create(handle_hash, handle_compare);
ws->bo_vas = util_hash_table_create(handle_hash, handle_compare);
(void) mtx_init(&ws->bo_handles_mutex, mtx_plain);
- (void) mtx_init(&ws->bo_va_mutex, mtx_plain);
+ (void) mtx_init(&ws->vm32.mutex, mtx_plain);
+ (void) mtx_init(&ws->vm64.mutex, mtx_plain);
(void) mtx_init(&ws->bo_fence_lock, mtx_plain);
- ws->va_offset = ws->va_start;
- list_inithead(&ws->va_holes);
+ list_inithead(&ws->vm32.holes);
+ list_inithead(&ws->vm64.holes);
+
+ /* The kernel currently returns 8MB. Make sure this doesn't change. */
+ if (ws->va_start > 8 * 1024 * 1024) {
+ /* Not enough 32-bit address space. */
+ radeon_winsys_destroy(&ws->base);
+ mtx_unlock(&fd_tab_mutex);
+ return NULL;
+ }
+
+ ws->vm32.start = ws->va_start;
+ ws->vm32.end = 1ull << 32;
+
+ /* The maximum is 8GB of virtual address space limited by the kernel.
+ * It's obviously not enough for bigger cards, like Hawaiis with 4GB
+ * and 8GB of physical memory and 4GB of GART.
+ *
+ * Older kernels set the limit to 4GB, which is even worse, so they only
+ * have 32-bit address space.
+ */
+ if (ws->info.drm_minor >= 41) {
+ ws->vm64.start = 1ull << 32;
+ ws->vm64.end = 1ull << 33;
+ }
/* TTM aligns the BO size to the CPU page size */
ws->info.gart_page_size = sysconf(_SC_PAGESIZE);
if (ws->num_cpus > 1 && debug_get_option_thread())
- util_queue_init(&ws->cs_queue, "radeon_cs", 8, 1);
+ util_queue_init(&ws->cs_queue, "radeon_cs", 8, 1, 0);
/* Create the screen at the end. The winsys must be initialized
* completely.
*
* Alternatively, we could create the screen based on "ws->gen"
* and link all drivers into one binary blob. */
- ws->base.screen = screen_create(&ws->base);
+ ws->base.screen = screen_create(&ws->base, config);
if (!ws->base.screen) {
radeon_winsys_destroy(&ws->base);
- pipe_mutex_unlock(fd_tab_mutex);
+ mtx_unlock(&fd_tab_mutex);
return NULL;
}
/* We must unlock the mutex once the winsys is fully initialized, so that
* other threads attempting to create the winsys from the same fd will
* get a fully initialized winsys and not just half-way initialized. */
- pipe_mutex_unlock(fd_tab_mutex);
+ mtx_unlock(&fd_tab_mutex);
return &ws->base;
fail_slab:
- if (ws->info.has_virtual_memory)
+ if (ws->info.r600_has_virtual_memory)
pb_slabs_deinit(&ws->bo_slabs);
fail_cache:
pb_cache_deinit(&ws->bo_cache);
fail1:
- pipe_mutex_unlock(fd_tab_mutex);
+ mtx_unlock(&fd_tab_mutex);
if (ws->surf_man)
radeon_surface_manager_free(ws->surf_man);
if (ws->fd >= 0)
projects / mesa.git / blobdiff