tidyup

[ieee754fpu.git] / src / ieee754 / fpdiv / div0.py

diff --git a/src/ieee754/fpdiv/div0.py b/src/ieee754/fpdiv/div0.py
index 68546007dd36ec6678032309d0cf03c9298b418d..34d7529fdf9c7d4f8b7080d47da7b31e04585df9 100644 (file)
--- a/src/ieee754/fpdiv/div0.py
+++ b/src/ieee754/fpdiv/div0.py
@@ -3,7 +3,7 @@
 Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
 """
 
-from nmigen import Module, Signal, Cat, Elaboratable
+from nmigen import Module, Signal, Cat, Elaboratable, Const
 from nmigen.cli import main, verilog
 
 from ieee754.fpcommon.fpbase import (FPNumBaseRecord, Overflow)
@@ -54,26 +54,47 @@ class FPDivStage0Mod(Elaboratable):
             # do conversion here, of both self.i.a and self.i.b,
             # into DivPipeInputData dividend and divisor.
 
+            # XXX *sigh* magic constants...
+            if self.pspec.width == 16:
+                if self.pspec.log2_radix == 1:
+                    extra = 2
+                elif self.pspec.log2_radix == 3:
+                    extra = 2
+                else:
+                    extra = 3
+            elif self.pspec.width == 32:
+                if self.pspec.log2_radix == 1:
+                    extra = 3
+                else:
+                    extra = 4
+            elif self.pspec.width == 64:
+                if self.pspec.log2_radix == 1:
+                    extra = 2
+                elif self.pspec.log2_radix == 3:
+                    extra = 2
+                else:
+                    extra = 3
+
             # the mantissas, having been de-normalised (and containing
             # a "1" in the MSB) represent numbers in the range 0.5 to
             # 0.9999999-recurring.  the min and max range of the
             # result is therefore 0.4999999 (0.5/0.99999) and 1.9999998
             # (0.99999/0.5).
 
-            # zero-extend the mantissas (room for sticky/guard)
-            # plus the extra MSB.  See DivPipeBaseStage.get_core_config
+            # zero-extend the mantissas (room for sticky/round/guard)
+            # plus the extra MSB.
             am0 = Signal(len(self.i.a.m)+3, reset_less=True)
             bm0 = Signal(len(self.i.b.m)+3, reset_less=True)
             m.d.comb += [
-                         am0.eq(Cat(0, 0, self.i.a.m, 0)),
-                         bm0.eq(Cat(0, 0, self.i.b.m, 0))
+                         am0.eq(Cat(0,0,0,self.i.a.m, 0)),
+                         bm0.eq(Cat(0,0,0,self.i.b.m, 0)),
                         ]
 
             m.d.comb += [self.o.z.e.eq(self.i.a.e - self.i.b.e + 1),
                          self.o.z.s.eq(self.i.a.s ^ self.i.b.s),
-                         self.o.dividend.eq(am0), # TODO: check
-                         self.o.divisor_radicand.eq(bm0), # TODO: check
-                         self.o.operation.eq(Const(0)) # TODO check: DIV
+                         self.o.dividend[len(self.i.a.m)+extra:].eq(am0),
+                         self.o.divisor_radicand.eq(bm0),
+                         self.o.operation.eq(Const(0)) # XXX DIV operation
                 ]
 
         # these are required and must not be touched