unsigned int level, unsigned int layer,
enum isl_format format, bool is_render_target)
{
+ memset(info, 0, sizeof(*info));
assert(level < surf->surf->levels);
assert(layer < MAX2(surf->surf->logical_level0_px.depth >> level,
surf->surf->logical_level0_px.array_len));
if (format == ISL_FORMAT_UNSUPPORTED)
format = surf->surf->format;
- if (format == ISL_FORMAT_R24_UNORM_X8_TYPELESS) {
- /* Unfortunately, ISL_FORMAT_R24_UNORM_X8_TYPELESS it isn't supported as
- * a render target, which would prevent us from blitting to 24-bit
- * depth. The miptree consists of 32 bits per pixel, arranged as 24-bit
- * depth values interleaved with 8 "don't care" bits. Since depth
- * values don't require any blending, it doesn't matter how we interpret
- * the bit pattern as long as we copy the right amount of data, so just
- * map it as 8-bit BGRA.
- */
- format = ISL_FORMAT_B8G8R8A8_UNORM;
- }
-
info->surf = *surf->surf;
info->addr = surf->addr;
if (info->aux_usage != ISL_AUX_USAGE_NONE) {
info->aux_surf = *surf->aux_surf;
info->aux_addr = surf->aux_addr;
- assert(level < info->aux_surf.levels);
- assert(layer < MAX2(info->aux_surf.logical_level0_px.depth >> level,
- info->aux_surf.logical_level0_px.array_len));
}
info->clear_color = surf->clear_color;
*/
if (is_render_target && blorp->isl_dev->info->gen <= 6)
info->view.array_len = MIN2(info->view.array_len, 512);
+
+ if (surf->tile_x_sa || surf->tile_y_sa) {
+ /* This is only allowed on simple 2D surfaces without MSAA */
+ assert(info->surf.dim == ISL_SURF_DIM_2D);
+ assert(info->surf.samples == 1);
+ assert(info->surf.levels == 1);
+ assert(info->surf.logical_level0_px.array_len == 1);
+ assert(info->aux_usage == ISL_AUX_USAGE_NONE);
+
+ info->tile_x_sa = surf->tile_x_sa;
+ info->tile_y_sa = surf->tile_y_sa;
+
+ /* Instead of using the X/Y Offset fields in RENDER_SURFACE_STATE, we
+ * place the image at the tile boundary and offset our sampling or
+ * rendering. For this reason, we need to grow the image by the offset
+ * to ensure that the hardware doesn't think we've gone past the edge.
+ */
+ info->surf.logical_level0_px.w += surf->tile_x_sa;
+ info->surf.logical_level0_px.h += surf->tile_y_sa;
+ info->surf.phys_level0_sa.w += surf->tile_x_sa;
+ info->surf.phys_level0_sa.h += surf->tile_y_sa;
+ }
}
memset(wm_key, 0, sizeof(*wm_key));
wm_key->nr_color_regions = 1;
for (int i = 0; i < MAX_SAMPLERS; i++)
- wm_key->tex.swizzles[i] = SWIZZLE_XYZW;
+ wm_key->base.tex.swizzles[i] = SWIZZLE_XYZW;
}
const unsigned *
wm_prog_data->base.nr_params = 0;
wm_prog_data->base.param = NULL;
- /* BLORP always just uses the first two binding table entries */
- wm_prog_data->binding_table.render_target_start = BLORP_RENDERBUFFER_BT_INDEX;
+ /* BLORP always uses the first two binding table entries:
+ * - Surface 0 is the render target (which always start from 0)
+ * - Surface 1 is the source texture
+ */
wm_prog_data->base.binding_table.texture_start = BLORP_TEXTURE_BT_INDEX;
- nir = brw_preprocess_nir(compiler, nir);
+ brw_preprocess_nir(compiler, nir, NULL);
nir_remove_dead_variables(nir, nir_var_shader_in);
nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
const unsigned *program =
brw_compile_fs(compiler, blorp->driver_ctx, mem_ctx, wm_key,
- wm_prog_data, nir, NULL, -1, -1, false, use_repclear,
- NULL, NULL);
+ wm_prog_data, nir, -1, -1, -1, false, use_repclear,
+ NULL, NULL, NULL);
return program;
}
nir->options =
compiler->glsl_compiler_options[MESA_SHADER_VERTEX].NirOptions;
- nir = brw_preprocess_nir(compiler, nir);
+ brw_preprocess_nir(compiler, nir, NULL);
nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
vs_prog_data->inputs_read = nir->info.inputs_read;
const unsigned *program =
brw_compile_vs(compiler, blorp->driver_ctx, mem_ctx,
- &vs_key, vs_prog_data, nir, -1, NULL);
+ &vs_key, vs_prog_data, nir, -1, NULL, NULL);
return program;
}
};
bool
-blorp_ensure_sf_program(struct blorp_context *blorp,
+blorp_ensure_sf_program(struct blorp_batch *batch,
struct blorp_params *params)
{
+ struct blorp_context *blorp = batch->blorp;
const struct brw_wm_prog_data *wm_prog_data = params->wm_prog_data;
assert(params->wm_prog_data);
memcpy(key.key.interp_mode, wm_prog_data->interp_mode,
sizeof(key.key.interp_mode));
- if (blorp->lookup_shader(blorp, &key, sizeof(key),
+ if (blorp->lookup_shader(batch, &key, sizeof(key),
¶ms->sf_prog_kernel, ¶ms->sf_prog_data))
return true;
&prog_data_tmp, &vue_map, &program_size);
bool result =
- blorp->upload_shader(blorp, &key, sizeof(key), program, program_size,
+ blorp->upload_shader(batch, &key, sizeof(key), program, program_size,
(void *)&prog_data_tmp, sizeof(prog_data_tmp),
¶ms->sf_prog_kernel, ¶ms->sf_prog_data);
void
blorp_hiz_op(struct blorp_batch *batch, struct blorp_surf *surf,
uint32_t level, uint32_t start_layer, uint32_t num_layers,
- enum blorp_hiz_op op)
+ enum isl_aux_op op)
{
struct blorp_params params;
blorp_params_init(¶ms);
batch->blorp->exec(batch, ¶ms);
}
}
+
+void
+blorp_hiz_stencil_op(struct blorp_batch *batch, struct blorp_surf *stencil,
+ uint32_t level, uint32_t start_layer,
+ uint32_t num_layers, enum isl_aux_op op)
+{
+ struct blorp_params params;
+ blorp_params_init(¶ms);
+
+ params.hiz_op = op;
+ params.full_surface_hiz_op = true;
+
+ for (uint32_t a = 0; a < num_layers; a++) {
+ const uint32_t layer = start_layer + a;
+
+ brw_blorp_surface_info_init(batch->blorp, ¶ms.stencil, stencil, level,
+ layer, stencil->surf->format, true);
+ params.x1 = minify(params.stencil.surf.logical_level0_px.width,
+ params.stencil.view.base_level);
+ params.y1 = minify(params.stencil.surf.logical_level0_px.height,
+ params.stencil.view.base_level);
+ params.dst.surf.samples = params.stencil.surf.samples;
+ params.dst.surf.logical_level0_px =
+ params.stencil.surf.logical_level0_px;
+ params.dst.view = params.stencil.view;
+ params.num_samples = params.stencil.surf.samples;
+
+ batch->blorp->exec(batch, ¶ms);
+ }
+}
projects / mesa.git / blobdiff