#include "program/prog_instruction.h"
#include "blorp_priv.h"
-#include "brw_compiler.h"
-#include "brw_nir.h"
+#include "compiler/brw_compiler.h"
+#include "compiler/brw_nir.h"
void
blorp_init(struct blorp_context *blorp, void *driver_ctx,
* map it as 8-bit BGRA.
*/
format = ISL_FORMAT_B8G8R8A8_UNORM;
- } else if (surf->surf->usage & ISL_SURF_USAGE_STENCIL_BIT) {
- assert(surf->surf->format == ISL_FORMAT_R8_UINT);
- /* Prior to Broadwell, we can't render to R8_UINT */
- if (blorp->isl_dev->info->gen < 8)
- format = ISL_FORMAT_R8_UNORM;
}
info->surf = *surf->surf;
info->z_offset = 0;
}
- /* Sandy Bridge has a limit of a maximum of 512 layers for layered
- * rendering.
+ /* Sandy Bridge and earlier have a limit of a maximum of 512 layers for
+ * layered rendering.
*/
- if (is_render_target && blorp->isl_dev->info->gen == 6)
+ if (is_render_target && blorp->isl_dev->info->gen <= 6)
info->view.array_len = MIN2(info->view.array_len, 512);
}
blorp_params_init(struct blorp_params *params)
{
memset(params, 0, sizeof(*params));
+ params->num_samples = 1;
params->num_draw_buffers = 1;
params->num_layers = 1;
}
wm_key->tex.swizzles[i] = SWIZZLE_XYZW;
}
-static int
-nir_uniform_type_size(const struct glsl_type *type)
-{
- /* Only very basic types are allowed */
- assert(glsl_type_is_vector_or_scalar(type));
- assert(glsl_get_bit_size(type) == 32);
-
- return glsl_get_vector_elements(type) * 4;
-}
-
const unsigned *
-brw_blorp_compile_nir_shader(struct blorp_context *blorp, struct nir_shader *nir,
- const struct brw_wm_prog_key *wm_key,
- bool use_repclear,
- struct brw_blorp_prog_data *prog_data,
- unsigned *program_size)
+blorp_compile_fs(struct blorp_context *blorp, void *mem_ctx,
+ struct nir_shader *nir,
+ struct brw_wm_prog_key *wm_key,
+ bool use_repclear,
+ struct brw_wm_prog_data *wm_prog_data,
+ unsigned *program_size)
{
const struct brw_compiler *compiler = blorp->compiler;
- void *mem_ctx = ralloc_context(NULL);
-
- /* Calling brw_preprocess_nir and friends is destructive and, if cloning is
- * enabled, may end up completely replacing the nir_shader. Therefore, we
- * own it and might as well put it in our context for easy cleanup.
- */
- ralloc_steal(mem_ctx, nir);
nir->options =
compiler->glsl_compiler_options[MESA_SHADER_FRAGMENT].NirOptions;
- struct brw_wm_prog_data wm_prog_data;
- memset(&wm_prog_data, 0, sizeof(wm_prog_data));
+ memset(wm_prog_data, 0, sizeof(*wm_prog_data));
- wm_prog_data.base.nr_params = 0;
- wm_prog_data.base.param = NULL;
+ assert(exec_list_is_empty(&nir->uniforms));
+ wm_prog_data->base.nr_params = 0;
+ wm_prog_data->base.param = NULL;
/* BLORP always just uses the first two binding table entries */
- wm_prog_data.binding_table.render_target_start = BLORP_RENDERBUFFER_BT_INDEX;
- wm_prog_data.base.binding_table.texture_start = BLORP_TEXTURE_BT_INDEX;
+ wm_prog_data->binding_table.render_target_start = BLORP_RENDERBUFFER_BT_INDEX;
+ wm_prog_data->base.binding_table.texture_start = BLORP_TEXTURE_BT_INDEX;
nir = brw_preprocess_nir(compiler, nir);
nir_remove_dead_variables(nir, nir_var_shader_in);
nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
- /* Uniforms are required to be lowered before going into compile_fs. For
- * BLORP, we'll assume that whoever builds the shader sets the location
- * they want so we just need to lower them and figure out how many we have
- * in total.
- */
- nir->num_uniforms = 0;
- nir_foreach_variable(var, &nir->uniforms) {
- var->data.driver_location = var->data.location;
- unsigned end = var->data.location + nir_uniform_type_size(var->type);
- nir->num_uniforms = MAX2(nir->num_uniforms, end);
+ if (blorp->compiler->devinfo->gen < 6) {
+ if (nir->info.fs.uses_discard)
+ wm_key->iz_lookup |= BRW_WM_IZ_PS_KILL_ALPHATEST_BIT;
+
+ wm_key->input_slots_valid = nir->info.inputs_read | VARYING_BIT_POS;
}
- nir_lower_io(nir, nir_var_uniform, nir_uniform_type_size, 0);
const unsigned *program =
brw_compile_fs(compiler, blorp->driver_ctx, mem_ctx, wm_key,
- &wm_prog_data, nir, NULL, -1, -1, false, use_repclear,
+ wm_prog_data, nir, NULL, -1, -1, false, use_repclear,
NULL, program_size, NULL);
- /* Copy the relavent bits of wm_prog_data over into the blorp prog data */
- prog_data->dispatch_8 = wm_prog_data.dispatch_8;
- prog_data->dispatch_16 = wm_prog_data.dispatch_16;
- prog_data->first_curbe_grf_0 = wm_prog_data.base.dispatch_grf_start_reg;
- prog_data->first_curbe_grf_2 = wm_prog_data.dispatch_grf_start_reg_2;
- prog_data->ksp_offset_2 = wm_prog_data.prog_offset_2;
- prog_data->persample_msaa_dispatch = wm_prog_data.persample_dispatch;
- prog_data->flat_inputs = wm_prog_data.flat_inputs;
- prog_data->num_varying_inputs = wm_prog_data.num_varying_inputs;
- prog_data->inputs_read = nir->info->inputs_read;
+ return program;
+}
- assert(wm_prog_data.base.nr_params == 0);
+const unsigned *
+blorp_compile_vs(struct blorp_context *blorp, void *mem_ctx,
+ struct nir_shader *nir,
+ struct brw_vs_prog_data *vs_prog_data,
+ unsigned *program_size)
+{
+ const struct brw_compiler *compiler = blorp->compiler;
+
+ nir->options =
+ compiler->glsl_compiler_options[MESA_SHADER_VERTEX].NirOptions;
+
+ nir = brw_preprocess_nir(compiler, nir);
+ nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
+
+ vs_prog_data->inputs_read = nir->info.inputs_read;
+
+ brw_compute_vue_map(compiler->devinfo,
+ &vs_prog_data->base.vue_map,
+ nir->info.outputs_written,
+ nir->info.separate_shader);
+
+ struct brw_vs_prog_key vs_key = { 0, };
+
+ const unsigned *program =
+ brw_compile_vs(compiler, blorp->driver_ctx, mem_ctx,
+ &vs_key, vs_prog_data, nir,
+ NULL, false, -1, program_size, NULL);
return program;
}
+struct blorp_sf_key {
+ enum blorp_shader_type shader_type; /* Must be BLORP_SHADER_TYPE_GEN4_SF */
+
+ struct brw_sf_prog_key key;
+};
+
+bool
+blorp_ensure_sf_program(struct blorp_context *blorp,
+ struct blorp_params *params)
+{
+ const struct brw_wm_prog_data *wm_prog_data = params->wm_prog_data;
+ assert(params->wm_prog_data);
+
+ /* Gen6+ doesn't need a strips and fans program */
+ if (blorp->compiler->devinfo->gen >= 6)
+ return true;
+
+ struct blorp_sf_key key = {
+ .shader_type = BLORP_SHADER_TYPE_GEN4_SF,
+ };
+
+ /* Everything gets compacted in vertex setup, so we just need a
+ * pass-through for the correct number of input varyings.
+ */
+ const uint64_t slots_valid = VARYING_BIT_POS |
+ ((1ull << wm_prog_data->num_varying_inputs) - 1) << VARYING_SLOT_VAR0;
+
+ key.key.attrs = slots_valid;
+ key.key.primitive = BRW_SF_PRIM_TRIANGLES;
+ key.key.contains_flat_varying = wm_prog_data->contains_flat_varying;
+
+ STATIC_ASSERT(sizeof(key.key.interp_mode) ==
+ sizeof(wm_prog_data->interp_mode));
+ memcpy(key.key.interp_mode, wm_prog_data->interp_mode,
+ sizeof(key.key.interp_mode));
+
+ if (blorp->lookup_shader(blorp, &key, sizeof(key),
+ ¶ms->sf_prog_kernel, ¶ms->sf_prog_data))
+ return true;
+
+ void *mem_ctx = ralloc_context(NULL);
+
+ const unsigned *program;
+ unsigned program_size;
+
+ struct brw_vue_map vue_map;
+ brw_compute_vue_map(blorp->compiler->devinfo, &vue_map, slots_valid, false);
+
+ struct brw_sf_prog_data prog_data_tmp;
+ program = brw_compile_sf(blorp->compiler, mem_ctx, &key.key,
+ &prog_data_tmp, &vue_map, &program_size);
+
+ bool result =
+ blorp->upload_shader(blorp, &key, sizeof(key), program, program_size,
+ (void *)&prog_data_tmp, sizeof(prog_data_tmp),
+ ¶ms->sf_prog_kernel, ¶ms->sf_prog_data);
+
+ ralloc_free(mem_ctx);
+
+ return result;
+}
+
void
-blorp_gen6_hiz_op(struct blorp_batch *batch,
- struct blorp_surf *surf, unsigned level, unsigned layer,
- enum blorp_hiz_op op)
+blorp_hiz_op(struct blorp_batch *batch, struct blorp_surf *surf,
+ uint32_t level, uint32_t start_layer, uint32_t num_layers,
+ enum blorp_hiz_op op)
{
struct blorp_params params;
blorp_params_init(¶ms);
params.hiz_op = op;
- brw_blorp_surface_info_init(batch->blorp, ¶ms.depth, surf, level, layer,
- surf->surf->format, true);
-
- /* Align the rectangle primitive to 8x4 pixels.
- *
- * During fast depth clears, the emitted rectangle primitive must be
- * aligned to 8x4 pixels. From the Ivybridge PRM, Vol 2 Part 1 Section
- * 11.5.3.1 Depth Buffer Clear (and the matching section in the Sandybridge
- * PRM):
- * If Number of Multisamples is NUMSAMPLES_1, the rectangle must be
- * aligned to an 8x4 pixel block relative to the upper left corner
- * of the depth buffer [...]
- *
- * For hiz resolves, the rectangle must also be 8x4 aligned. Item
- * WaHizAmbiguate8x4Aligned from the Haswell workarounds page and the
- * Ivybridge simulator require the alignment.
- *
- * To be safe, let's just align the rect for all hiz operations and all
- * hardware generations.
- *
- * However, for some miptree slices of a Z24 texture, emitting an 8x4
- * aligned rectangle that covers the slice may clobber adjacent slices if
- * we strictly adhered to the texture alignments specified in the PRM. The
- * Ivybridge PRM, Section "Alignment Unit Size", states that
- * SURFACE_STATE.Surface_Horizontal_Alignment should be 4 for Z24 surfaces,
- * not 8. But commit 1f112cc increased the alignment from 4 to 8, which
- * prevents the clobbering.
- */
- params.x1 = minify(params.depth.surf.logical_level0_px.width,
- params.depth.view.base_level);
- params.y1 = minify(params.depth.surf.logical_level0_px.height,
- params.depth.view.base_level);
- params.x1 = ALIGN(params.x1, 8);
- params.y1 = ALIGN(params.y1, 4);
-
- if (params.depth.view.base_level == 0) {
- /* TODO: What about MSAA? */
- params.depth.surf.logical_level0_px.width = params.x1;
- params.depth.surf.logical_level0_px.height = params.y1;
+ for (uint32_t a = 0; a < num_layers; a++) {
+ const uint32_t layer = start_layer + a;
+
+ brw_blorp_surface_info_init(batch->blorp, ¶ms.depth, surf, level,
+ layer, surf->surf->format, true);
+
+ /* Align the rectangle primitive to 8x4 pixels.
+ *
+ * During fast depth clears, the emitted rectangle primitive must be
+ * aligned to 8x4 pixels. From the Ivybridge PRM, Vol 2 Part 1 Section
+ * 11.5.3.1 Depth Buffer Clear (and the matching section in the
+ * Sandybridge PRM):
+ *
+ * If Number of Multisamples is NUMSAMPLES_1, the rectangle must be
+ * aligned to an 8x4 pixel block relative to the upper left corner
+ * of the depth buffer [...]
+ *
+ * For hiz resolves, the rectangle must also be 8x4 aligned. Item
+ * WaHizAmbiguate8x4Aligned from the Haswell workarounds page and the
+ * Ivybridge simulator require the alignment.
+ *
+ * To be safe, let's just align the rect for all hiz operations and all
+ * hardware generations.
+ *
+ * However, for some miptree slices of a Z24 texture, emitting an 8x4
+ * aligned rectangle that covers the slice may clobber adjacent slices
+ * if we strictly adhered to the texture alignments specified in the
+ * PRM. The Ivybridge PRM, Section "Alignment Unit Size", states that
+ * SURFACE_STATE.Surface_Horizontal_Alignment should be 4 for Z24
+ * surfaces, not 8. But commit 1f112cc increased the alignment from 4 to
+ * 8, which prevents the clobbering.
+ */
+ params.x1 = minify(params.depth.surf.logical_level0_px.width,
+ params.depth.view.base_level);
+ params.y1 = minify(params.depth.surf.logical_level0_px.height,
+ params.depth.view.base_level);
+ params.x1 = ALIGN(params.x1, 8);
+ params.y1 = ALIGN(params.y1, 4);
+
+ if (params.depth.view.base_level == 0) {
+ /* TODO: What about MSAA? */
+ params.depth.surf.logical_level0_px.width = params.x1;
+ params.depth.surf.logical_level0_px.height = params.y1;
+ }
+
+ params.dst.surf.samples = params.depth.surf.samples;
+ params.dst.surf.logical_level0_px = params.depth.surf.logical_level0_px;
+ params.depth_format =
+ isl_format_get_depth_format(surf->surf->format, false);
+ params.num_samples = params.depth.surf.samples;
+
+ batch->blorp->exec(batch, ¶ms);
}
-
- params.dst.surf.samples = params.depth.surf.samples;
- params.dst.surf.logical_level0_px = params.depth.surf.logical_level0_px;
- params.depth_format = isl_format_get_depth_format(surf->surf->format, false);
-
- batch->blorp->exec(batch, ¶ms);
}
projects / mesa.git / blobdiff